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M7AFS1500-FGG676I

更新时间： 2024-11-12 14:43:19
品牌 Logo 应用领域
ACTEL 栅可编程逻辑
页数 文件大小 规格书
272页 3540K
描述
Field Programmable Gate Array, 1500000 Gates, CMOS, PBGA676, 1 MM PITCH, GREEN, FBGA-676

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M7AFS1500-FGG676I 技术参数

是否Rohs认证：符合生命周期：Obsolete
包装说明：1 MM PITCH, GREEN, FBGA-676Reach Compliance Code：compliant
风险等级：5.84Is Samacsys：N
JESD-30 代码：S-PBGA-B676JESD-609代码：e1
长度：23 mm湿度敏感等级：3
等效关口数量：1500000端子数量：676
最高工作温度：85 °C最低工作温度：-40 °C
组织：1500000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：250
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.44 mm最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：23 mmBase Number Matches：1

M7AFS1500-FGG676I 数据手册

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Advanced v0.8  
®
Fusion Family of Mixed-Signal Flash FPGAs  
®
with Optional Soft ARM Support  
Low Power Consumption  
Features and Benefits  
High-Performance Reprogrammable Flash Technology  
•
•
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator  
Sleep and Standby Low Power Modes  
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process  
Nonvolatile, Retains Program when Powered Off  
Live at Power-Up (LAPU) Single-Chip Solution  
350 MHz System Performance  
In-System Programming (ISP) and Security  
•
•
Secure ISP with 128-Bit AES via JTAG  
FlashLock to Secure FPGA Contents  
®
Advanced Digital I/O  
Embedded Flash Memory  
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /1.8 V /  
1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input  
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS  
•
User Flash Memory – 2 Mbits to 8 Mbits  
–
–
Configurable 8-, 16-, or 32-Bit Datapath  
10 ns Access in Read-Ahead Mode  
•
1 kbit of Additional FlashROM  
•
Integrated A/D Converter (ADC) and Analog I/O  
–
–
Built-In I/O Registers  
700 Mbps DDR Operation  
•
•
•
•
•
•
Up to 12-Bit Resolution and up to 600 ksps  
Internal 2.56 V or External Reference Voltage  
ADC: Up to 30 Scalable Analog Input Channels  
High-Voltage Input Tolerance: 12 V  
Current Monitor and Temperature Monitor Blocks  
Up to 10 MOSFET Gate Driver Outputs  
•
•
Hot-Swappable I/Os  
Programmable Output Slew Rate, Drive Strength, and Weak  
Pull-Up/Down Resistor  
•
Pin-Compatible Packages across the Fusion Family  
SRAMs and FIFOs  
–
–
P- and N-Channel Power MOSFET Support  
Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths  
•
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
On-Chip Clocking Support  
•
•
True Dual-Port SRAM (except ×18)  
Programmable Embedded FIFO Control Logic  
•
•
•
•
Internal 100 MHz RC Oscillator (accurate to 1%)  
Crystal Oscillator Support (32 kHz to 20 MHz)  
Programmable Real-Time Counter (RTC)  
Soft ARM7™ Core Support in M7 and M1 Fusion Devices  
•
CortexM1(without debug), CoreMP7Sd (with debug) and  
CoreMP7S (without debug)  
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs  
–
–
Phase Shift, Multiply/Divide, and Delay Capabilities  
Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz  
Table 1 •  
Fusion Family  
Fusion Devices  
AFS090  
AFS250  
AFS600  
AFS1500  
1
M7AFS600  
CoreMP7  
Cortex-M1  
ARM-Enabled  
Fusion Devices  
2
M1AFS250  
M1AFS600  
M1AFS1500  
System Gates  
90,000  
2,304  
Yes  
1
250,000  
6,144  
Yes  
1
600,000  
13,824  
Yes  
2
1,500,000  
Tiles (D-flip-flops)  
Secure (AES) ISP  
PLLs  
38,400  
Yes  
2
General  
Information  
Globals  
18  
1
18  
18  
18  
Flash Memory Blocks (2 Mbits)  
Total Flash Memory Bits  
FlashROM Bits  
1
2
4
2 M  
1 k  
6
2 M  
1 k  
8
4 M  
1 k  
24  
8 M  
1 k  
60  
Memory  
RAM Blocks (4,608 bits)  
RAM kbits  
27  
5
36  
108  
10  
270  
10  
Analog Quads  
6
Analog Input Channels  
Gate Driver Outputs  
I/O Banks (+ JTAG)  
Maximum Digital I/Os  
Analog I/Os  
15  
5
18  
30  
30  
6
10  
10  
Analog and I/Os  
4
4
5
5
75  
20  
114  
24  
172  
40  
252  
40  
Notes:  
1. Refer to the CoreMP7 datasheet for more information.  
2. Refer to the Cortex-M1 product brief for more information.  
June 2007  
i
© 2007 Actel Corporation  
See the Actel website for the latest version of the datasheet.  
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