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M74HC4094 PDF预览

M74HC4094

更新时间: 2024-11-23 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
12页 272K
描述
8 BIT SIPO SHIFT LATCH REGISTER 3-STATE

M74HC4094 数据手册

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M54HC4094  
M74HC4094  
8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)  
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HIGH SPEED  
fMAX = 73 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 4094B  
ORDER CODES :  
M54HC4094F1R  
M74HC4094B1R  
M74HC4094M1R  
M74HC4094C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC4094 is a high speed CMOS 8 BIT  
SIPOSHIFT LATCH REGISTERfabricated with sili-  
con gate C2MOS technology.  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
This device consists of an 8-bit shift register and an  
8-bit latch with 3-state output buffer. Data is shifted  
serially through the shift register on the positive  
going transition of the clock input signal. The output  
of the last stage (Qs) can be used to cascade sev-  
eral devices.  
Data on the Qs output is transferred to a second out-  
put (Qs’) on the following negative transition of the  
clockinput signal. The data of eachstage of the shift  
register is provided with a latch, which latches data  
on the negative going transition of the STROBE  
input signal. When the STROBE input is held high,  
datapropagates through the latchto a3-state output  
buffer.  
This buffer is enabled when OUTPUT ENABLE  
input is taken high. All inputs are equipped with pro-  
tectioncircuits against static discharge and transient  
excess voltage.  
NC =  
No Internal  
Connection  
February 1993  
1/12  

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