M74HC4094YTTR

更新时间： 2024-11-25 17:33:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		锁存器移位寄存器
页数	文件大小	规格书
12页	272K
描述
8位SIPO移位寄存器锁存器（3态）

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中文翻译

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数据手册

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M74HC4094YTTR 数据手册

M54HC4094

M74HC4094

8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)

HIGH SPEED

f_MAX= 73 MHz (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

|I_OH| = I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 4094B

ORDER CODES :

M54HC4094F1R

M74HC4094B1R

M74HC4094M1R

M74HC4094C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC4094 is a high speed CMOS 8 BIT

SIPOSHIFT LATCH REGISTERfabricated with sili-

con gate C²MOS technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

This device consists of an 8-bit shift register and an

8-bit latch with 3-state output buffer. Data is shifted

serially through the shift register on the positive

going transition of the clock input signal. The output

of the last stage (Qs) can be used to cascade sev-

eral devices.

Data on the Qs output is transferred to a second out-

put (Qs’) on the following negative transition of the

clockinput signal. The data of eachstage of the shift

on the negative going transition of the STROBE

input signal. When the STROBE input is held high,

datapropagates through the latchto a3-state output

buffer.

This buffer is enabled when OUTPUT ENABLE

input is taken high. All inputs are equipped with pro-

tectioncircuits against static discharge and transient

excess voltage.

NC =

No Internal

Connection

February 1993

1/12

12 3 4 5 6 7...12

中文翻译

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