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M74HC4060C1R PDF预览

M74HC4060C1R

更新时间: 2024-11-25 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 振荡器计数器
页数 文件大小 规格书
12页 259K
描述
14 STAGE BINARY COUNTER/OSCILLATOR

M74HC4060C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.82
其他特性:OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT计数方向:UP
系列:HC/UHJESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.9662 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:24000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
位数:14功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):75 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:8.9662 mm最小 fmax:24 MHz

M74HC4060C1R 数据手册

 浏览型号M74HC4060C1R的Datasheet PDF文件第2页浏览型号M74HC4060C1R的Datasheet PDF文件第3页浏览型号M74HC4060C1R的Datasheet PDF文件第4页浏览型号M74HC4060C1R的Datasheet PDF文件第5页浏览型号M74HC4060C1R的Datasheet PDF文件第6页浏览型号M74HC4060C1R的Datasheet PDF文件第7页 
M54HC4060  
M74HC4060  
14 STAGE BINARY COUNTER/OSCILLATOR  
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HIGH SPEED  
fMAX = 58 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 4060B  
ORDER CODES :  
M54HC4060F1R  
M74HC4060B1R  
M74HC4060M1R  
M74HC4060C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC4060 is a high speed CMOS 14-  
STAGE BINARY COUNTER/OSCILLATOR fabri-  
cated in silicon gate C2MOS technology. It has the  
same high speed performance of LSTTL combined  
with true CMOS low power consumption. It operates  
ten times faster than metal-gate C2MOS IC (4060B)  
with the same power dissipation.  
The oscillator configuration allows design of either  
RC or crystal oscillator circuits. A high level on the  
CLEAR accomplishes the reset function, i.e. all  
counter outputs are made low and the oscillator is  
disabled.  
A negative transition on the clock input increments  
the counter. Ten kinds of divided output are pro-  
vided ; 4 to 10 and 12 to 14 stage inclusive. The  
maximum division available at Q12 is 1/16384 f os-  
cillator.  
NC =  
No Internal  
Connection  
The Ø1 input and the CLEAR input are equipped  
with protection circuits against static discharge and  
transient excess voltage.  
March 1993  
1/12  

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