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M66010FP PDF预览

M66010FP

更新时间: 2024-11-30 22:46:35
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
5页 68K
描述
24-BIT I/O EXPANDER

M66010FP 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP32,.45
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.62JESD-30 代码:R-PDSO-G32
JESD-609代码:e0长度:20 mm
位数:24I/O 线路数量:24
端口数量:1端子数量:32
最高工作温度:75 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP32,.45封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:2/6 V
认证状态:Not Qualified座面最大高度:2.4 mm
子类别:Parallel IO Port最大供电电压:6 V
最小供电电压:2 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:8.4 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

M66010FP 数据手册

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MITSUBISHI DIGITALASSP
M66010FP/GP
24-BIT I/O EXPANDER  
DESCRIPTION  
PIN CONFIGURATION (TOP VIEW)  
M66010 Semiconductor Integrated Circuit inputs 24-bit data  
in series and outputs it in parallel and vice versa, using shift  
register function.  
Equipped with 2 independent shift registers, one for serial-to-  
parallel, the other for parallel-to-serial, this IC is able to read  
serial input data into a shift register while converting data  
from parallel to serial. Parallel input/output pins are set to in-  
put or output according to the bit.  
The M66010 is useful in a wide range of applications, such as  
MCU (micro controller unit) input/output port extension and  
serial bus system data communication.  
SERIAL DATA OUTPUT  
SERIAL DATA INPUT  
CLOCK INPUT  
CHIP SELECT INPUT  
D0  
D1  
1
2
DO  
DI  
D1  
D2  
32 D1  
31 D2  
30 D3  
29 D4  
28 D5  
27 D6  
26 D7  
25 D8  
24 D9  
23 D10  
22 D11  
21 D12  
20 D13  
19 D14  
18 D15  
17 D16  
CLK  
CS  
3
CLK D3  
4
CS  
D4  
D5  
D6  
D7  
V
CC  
5
SET INPUT  
S
6
S
GND  
D24  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
GND  
7
PARALLEL  
DATA  
I/O  
8
D24 D8  
D23 D9  
D22 D10  
D21 D11  
D20 D12  
D19 D13  
D18 D14  
D17 D15  
D16  
FEATURES  
9
• Two-way serial data communication with MCU  
• Serial data intake possible during parallel-to-serial conver-  
sion  
• Parallel input/output switchable according to the bit  
• Low power dissipation: 100µW maximum per package  
(VCC =5V, Ta = 25˚C, quiescent)  
10  
11  
12  
13  
14  
15  
16  
PARALLEL  
DATA  
I/O  
• Schmidt input (DI, CLK, S, CS)  
• Open drain output (DO, D1 thru D24)  
• Parallel data input and output (D1 thru D24)  
• Wide operating supply voltage range (VCC = 2V ~ 6V)  
Outline 32P2W-A  
32P2U-B  
APPLICATION  
MCU-related serial-parallel data conversion, serial bus con-  
trol by MCU, etc.  
OPERATION  
FUNCTION  
(1)When power is turned on, the status of pins D0 and D1  
thru D24 is unstable. Their status turns high-impedance  
when S is shifted to “L”.  
(2)At CS fall edges, the status of pins D1 thru D24 is loaded  
on shift register 1.  
(3)At CLK fall edges, 24-bit data loaded as described above  
is output in series from pin D0.  
(4)At CLK rise edges, 24-bit serial data is taken in from pin  
DI and written on shift register 2.  
The M66010 is produced by using the silicon gate CMOS  
(complementary metal-oxide semiconductor) technology. It is  
distinguished for low power dissipation and high noise resis-  
tance.  
Because two independent shift registers are built in, one for  
serial-to-parallel, the other for parallel-to-serial, this IC is able  
to read serial input data into a shift register while converting  
parallel data into serial data.  
One cycle of latching 24-bit parallel data and outputing it in  
series while taking in serial data from MCU is initiated by  
CS’s shift from “H” to “L”. At CS fall edges, 24-bit parallel data  
is latched, and output in series from pin DO synchronously  
with shift clock fall edges. At shift clock rise edges, serial data  
is taken in from MCU via pin DI. The data is read into shift reg-  
ister. The 25th and following shift clock pulses are ignored  
and read-in operation is masked. The pin D0 status shifts to  
high-impedance. As CS is then shifted from “L” to “H”, 24-bit  
serial data taken in via pin DI is output in parallel to pins D1  
thru D24. Because parallel output pins are the n-channel  
open drain output type, write data “H” for pins which should  
be set to input.  
(5)The 25th and following CLK pulses are ignored, and serial  
data write is discontinued. Pin D0 status turns high-imped-  
ance.  
(6)At CS rise edges, data written as described in (4) is output  
to pins D1 thru D24.  
(7)Shift register 1 loads data added from outside as well as  
AND tie data which has the same contents as data latched  
by serial output latch.  
(8)If the CS rises before CLK reaches the 24th bit, parallel  
output latch latches data which has been written on shift  
register, and output it to pins D1 thru D24.  
(9)Pins D1 thru D24 are switched between input and output  
according to serial data input to pin DI. Pins for which “H”  
is written are set to input.  
1

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