Datasheet > M5-192/104-6AC

M5-192/104-6AC

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
47页	1091K
描述
Fifth Generation MACH Architecture

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M5-192/104-6AC 数据手册

Table 2. MACH 5 Speed Grades

Speed Grade

-10

Device

-5

-6

-7

-12

C, I

-15

C, I

-20

M5-128

C, I

M5-128/1

M5LV-128

M5-192/1

C, I

C,I

C, I

M5-256

C, I

M5-256/1

M5LV-256

M5-320

C, I

M5LV-320

M5-384

C, I

M5LV-384

M5-512

C, I

M5LV-512

C, I

Note:

1. C = Commercial grade, I = Industrial grade

2. /1 version recommended for new designs

3. Preliminary speciﬁcatons

With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512

macrocells to support full system logic integration. Extensive routing resources ensure pinout

retention as well as high utilization. It is ideal for PAL block device integration and a wide range

of other applications including high-speed computing, low-power applications, communications,

and embedded control. At each macrocell density point, Lattice offers several I/O and package

options to meet a wide range of design needs (Table 3).

Table 3. MACH 5 Package and I/O Options

M5-128/1

M5LV-128

M5-256/1

M5LV-256

M5-320

M5LV-320

M5-384

M5LV-384

M5-512

M5LV-512

M5-192/1

Supply Voltage

100-pin TQFP

100-pin PQFP

144-pin TQFP

144-pin PQFP

160-pin PQFP

208-pin PQFP

240-pin PQFP

256-ball BGA

352-ball BGA

3.3

68, 74

68*

3.3

68*, 74

3.3

68*

104

120

104*

120

104*

120

104*

120

104*

120

120*

160

120

160

120*

160

120

160

120*

160

120

160

184*

192

184*

192*

184*

192*

184*

192*

184*

192*

256

184*

192*

256

Note:

1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.

MACH 5 Family

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