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M4A5-32/32-7JNC PDF预览

M4A5-32/32-7JNC

更新时间: 2024-10-28 19:15:35
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
62页 784K
描述
EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44

M4A5-32/32-7JNC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ, LDCC44,.7SQ针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:8.53
其他特性:YES最大时钟频率:76.9 MHz
系统内可编程:YESJESD-30 代码:S-PQCC-J44
JESD-609代码:e3JTAG BST:YES
长度:16.5862 mm湿度敏感等级:3
专用输入次数:I/O 线路数量:32
宏单元数:32端子数量:44
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 32 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
电源:5 V可编程逻辑类型:EE PLD
传播延迟:7.5 ns认证状态:Not Qualified
座面最大高度:4.572 mm子类别:Programmable Logic Devices
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:16.5862 mm
Base Number Matches:1

M4A5-32/32-7JNC 数据手册

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ispMACH4A CPLD Family  
High Performance E2CMOS®  
Le a d -  
e e  
Fr  
In-System Programmable Logic  
P a c k a g e  
Op t io n s  
a ila b le !  
v
A
FEATURES  
2
High-performance, E CMOS 3.3-V & 5-V CPLD families  
Flexible architecture for rapid logic designs  
TM  
— Excellent First-Time-Fit and ret feature  
— SpeedLocking performance for guaranteed xed timing  
TM  
— Central, input and output switch matrices for 100% routability and 100% pin-out retention  
High speed  
— 5.0ns t Commercial and 7.5ns t Industrial  
PD  
PD  
— 182MHz f  
CNT  
32 to 512 macrocells; 32 to 768 registers  
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages  
Flexible architecture for a wide range of design styles  
— D/T registers and latches  
— Synchronous or asynchronous mode  
— Dedicated input registers  
— Programmable polarity  
— Reset/ preset swapping  
Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— JTAG (IEEE 1149.1) compliant for boundary scan testing  
— 3.3-V & 5-V JTAG in-system programming  
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system designs  
TM  
— Programmable pull-up or Bus-Friendly inputs and I/Os  
— Hot-socketing  
— Programmable security bit  
— Individual output slew rate control  
2
Advanced E CMOS process provides high-performance, cost-effective solutions  
Lead-free package options  
Publication# ISPM4A Rev: M  
Amendment/0  
Issue Date: September 2006  

M4A5-32/32-7JNC 替代型号

型号 品牌 替代类型 描述 数据表
M4A5-32/32-10JNI LATTICE

类似代替

EE PLD, 10ns, 32-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44

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