Datasheet > M4A3-512/256-7FANC

M4A3-512/256-7FANC

更新时间： 2024-10-31 04:54:55

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
62页	1081K
描述
EE PLD, 7.5ns, CMOS, PBGA388, FPBGA-388

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ispMACH^™4A CPLD Family

High Performance E²CMOS^®

Le a d -

e e

In-System Programmable Logic

P a c k a g e

Op t io n s

a ila b le !

FEATURES

◆ High-performance, E CMOS 3.3-V & 5-V CPLD families

◆ Flexible architecture for rapid logic designs

— Excellent First-Time-Fit and reﬁt feature

— SpeedLocking performance for guaranteed ﬁxed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆ High speed

— 5.0ns t Commercial and 7.5ns t Industrial

— 182MHz f

CNT

◆ 32 to 512 macrocells; 32 to 768 registers

◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆ Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— Programmable polarity

— Reset/ preset swapping

◆ Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— JTAG (IEEE 1149.1) compliant for boundary scan testing

— 3.3-V & 5-V JTAG in-system programming

— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system designs

— Programmable pull-up or Bus-Friendly inputs and I/Os

— Hot-socketing

— Programmable security bit

— Individual output slew rate control

◆ Advanced E CMOS process provides high-performance, cost-effective solutions

◆ Lead-free package options

Publication# ISPM4A Rev: M

Amendment/0

Issue Date: September 2006

12 3 4 5 6 7...62

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