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M4A3-128/64-7CANC PDF预览

M4A3-128/64-7CANC

更新时间: 2024-10-30 06:07:51
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
62页 1081K
描述
EE PLD, 7.5ns, CMOS, PBGA100, CABGA-100

M4A3-128/64-7CANC 数据手册

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ispMACH4A CPLD Family  
High Performance E2CMOS®  
Le a d -  
e e  
Fr  
In-System Programmable Logic  
P a c k a g e  
Op t io n s  
a ila b le !  
v
A
FEATURES  
2
High-performance, E CMOS 3.3-V & 5-V CPLD families  
Flexible architecture for rapid logic designs  
TM  
— Excellent First-Time-Fit and ret feature  
— SpeedLocking performance for guaranteed xed timing  
TM  
— Central, input and output switch matrices for 100% routability and 100% pin-out retention  
High speed  
— 5.0ns t Commercial and 7.5ns t Industrial  
PD  
PD  
— 182MHz f  
CNT  
32 to 512 macrocells; 32 to 768 registers  
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages  
Flexible architecture for a wide range of design styles  
— D/T registers and latches  
— Synchronous or asynchronous mode  
— Dedicated input registers  
— Programmable polarity  
— Reset/ preset swapping  
Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— JTAG (IEEE 1149.1) compliant for boundary scan testing  
— 3.3-V & 5-V JTAG in-system programming  
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system designs  
TM  
— Programmable pull-up or Bus-Friendly inputs and I/Os  
— Hot-socketing  
— Programmable security bit  
— Individual output slew rate control  
2
Advanced E CMOS process provides high-performance, cost-effective solutions  
Lead-free package options  
Publication# ISPM4A Rev: M  
Amendment/0  
Issue Date: September 2006  

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