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M48Z30 PDF预览

M48Z30

更新时间: 2024-09-24 22:25:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 静态存储器
页数 文件大小 规格书
12页 102K
描述
CMOS 32K x 8 ZEROPOWER SRAM

M48Z30 数据手册

 浏览型号M48Z30的Datasheet PDF文件第2页浏览型号M48Z30的Datasheet PDF文件第3页浏览型号M48Z30的Datasheet PDF文件第4页浏览型号M48Z30的Datasheet PDF文件第5页浏览型号M48Z30的Datasheet PDF文件第6页浏览型号M48Z30的Datasheet PDF文件第7页 
M48Z30  
M48Z30Y  
CMOS 32K x 8 ZEROPOWER SRAM  
INTEGRATED LOW POWER SRAM,  
POWER-FAIL CONTROL CIRCUIT and  
BATTERY  
CONVENTIONAL SRAM OPERATION;  
UNLIMITED WRITE CYCLES  
10 YEARS of DATA RETENTION in the  
ABSENCE of POWER  
28  
PIN and FUNCTION COMPATIBLE with  
JEDEC STANDARD 32K x 8 SRAMs  
1
AUTOMATIC POWER-FAIL CHIP DESELECT  
and WRITE PROTECTION  
PMDIP28 (PM)  
Module  
CHOICE of TWO WRITE PROTECT  
VOLTAGES:  
– M48Z30: 4.5V VPFD 4.75V  
– M48Z30Y: 4.2V VPFD 4.50V  
Figure 1. Logic Diagram  
BATTERY INTERNALLY ISOLATEDUNTIL  
POWER IS APPLIED  
DESCRIPTION  
The M48Z30/30Y 32K x 8 ZEROPOWER RAM is  
a non-volatile262,144 bit Static RAM organizedas  
32,768 words by 8 bits. The device combines an  
internal lithium battery and a full CMOS SRAM in a  
plastic 28 pin DIP Module. The ZEROPOWER  
Table 1. Signal Names  
A0 - A14  
Address Inputs  
Data Inputs / Outputs  
Chip Enable  
DQ0 - DQ7  
E
G
Output Enable  
Write Enable  
Supply Voltage  
Ground  
W
VCC  
VSS  
July 1994  
1/12  

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