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M48C260 PDF预览

M48C260

更新时间: 2024-11-13 21:19:43
品牌 Logo 应用领域
TEMIC 光电二极管外围集成电路
页数 文件大小 规格书
51页 562K
描述
Microprocessor Circuit, CMOS, PDSO28, SSO-28

M48C260 技术参数

生命周期:Transferred包装说明:SSO-28
Reach Compliance Code:unknown风险等级:5.65
JESD-30 代码:R-PDSO-G28端子数量:28
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
表面贴装:YES技术:CMOS
端子形式:GULL WING端子位置:DUAL
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

M48C260 数据手册

 浏览型号M48C260的Datasheet PDF文件第2页浏览型号M48C260的Datasheet PDF文件第3页浏览型号M48C260的Datasheet PDF文件第4页浏览型号M48C260的Datasheet PDF文件第5页浏览型号M48C260的Datasheet PDF文件第6页浏览型号M48C260的Datasheet PDF文件第7页 
M44C260/M48C260  
MARC4 – 4-bit Microcontroller  
The M44C260 and M48C260 are members of the TEMIC family of 4-bit single chip microcontrollers. The M48C260  
is the user programmable version of the M44C260. It contains an EEPROM program memory instead of a ROM. Both  
microcontroller types contain RAM, EEPROM data memory, parallel I/O ports, one timer with watchdog function, two  
8/16-bit multifunction timer/counter and the on-chip clock generation.  
Features  
Benefits  
4-bit HARVARD architecture  
Low power consumption  
1 µs instruction cycle  
Power-down mode < 1 µA  
4K 8-bit application program memory  
256 4-bit RAM  
2.4 to 6.2 V supply voltage  
Self-test functions  
16 8-bit EEPROM  
High-level programming language in qFORTH  
User programmable with the application program  
16 bidirectional I/O’s  
8 hard and software interrupt levels  
2
8-bit multifunction timer/counter  
Interval timer with watchdog  
32 kHz on-chip oscillator  
V
V
NWP  
NRST  
TE  
TCL  
OSCIN  
OSCOUT  
SS  
DD  
Test  
Reset  
Clock  
Sleep  
Timer 2  
Timer 1  
ROM or  
EEPROM  
4K x 8 bit  
RAM  
256 x 4 bit  
Watch-  
dog  
EEPROM  
16 x 8 bit  
Timer B  
Timer A  
MARC4  
4–bit CPU core  
Intervall  
timer  
I/O bus  
Input  
Port 4  
Interrupt  
inputs  
I/O  
I/O  
I/O  
I/O  
INT6  
94 9038  
Port 0  
Port 1  
Port 2  
Port 3  
TA TB  
IP43  
IP40  
Figure 1. Block diagram  
TELEFUNKEN Semiconductors  
1 (51)  
Rev. A2, 16-Dec-97  
Preliminary Information  

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