Datasheet > 存储 > DRAM> M381L3223DTM-LCC

M381L3223DTM-LCC

更新时间： 2024-01-23 05:05:07

品牌	Logo	应用领域
三星 - SAMSUNG		存储内存集成电路动态存储器双倍数据速率时钟
页数	文件大小	规格书
22页	355K
描述
184pin Unbuffered Module based on 256Mb D-die 64/72-bit Non ECC/ECC

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技术参数
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M381L3223DTM-LCC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	DIMM, DIMM184	Reach Compliance Code：	unknown
风险等级：	5.84	最长访问时间：	0.65 ns
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PDMA-N184	内存密度：	2415919104 bit
内存集成电路类型：	DDR DRAM MODULE	内存宽度：	72
端子数量：	184	字数：	33554432 words
字数代码：	32000000	最高工作温度：	70 °C
最低工作温度：		组织：	32MX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIMM	封装等效代码：	DIMM184
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
电源：	2.6 V	认证状态：	Not Qualified
刷新周期：	8192	子类别：	DRAMs
最大压摆率：	2.7 mA	标称供电电压 (Vsup)：	2.6 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

M381L3223DTM-LCC 数据手册

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128MB, 256MB, 512MB Unbuffered DIMM

DDR SDRAM

System Notes :

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Test point

Output

50Ω

VSSQ

Figure 1 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

VDDQ

50Ω

Output

Test point

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

For Maximum slew rate, only one DQ is switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.6V, typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.5V, slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and

voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divces only.

h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5

V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or

VIH(DC) to VIL(DC), similarly for rising transitions.

i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.

Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the

slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as:

{1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

Rev. 1.2 May. 2003

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中文翻译

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与M381L3223DTM-LCC相关器件

型号	品牌	描述	获取价格	数据表
M381L3223DTM-LCC/C4	SAMSUNG	184pin Unbuffered Module based on 256Mb D-die 64/72-bit Non ECC/ECC	获取价格
M381L3223ETM-A2	SAMSUNG	DDR SDRAM Unbuffered Module	获取价格
M381L3223ETM-AA	SAMSUNG	DDR SDRAM Unbuffered Module	获取价格
M381L3223ETM-B0	SAMSUNG	DDR SDRAM Unbuffered Module	获取价格
M381L3223ETM-CB3	SAMSUNG	DDR SDRAM Unbuffered Module	获取价格
M381L3223ETM-CC5	SAMSUNG	184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC	获取价格

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