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M366S1623ETS-C1L PDF预览

M366S1623ETS-C1L

更新时间: 2024-01-14 05:10:17
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
11页 168K
描述
Synchronous DRAM Module, 16MX64, 6ns, CMOS, DIMM-168

M366S1623ETS-C1L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM168
针数:168Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.92访问模式:DUAL BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:1073741824 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:64
湿度敏感等级:1功能数量:1
端口数量:1端子数量:168
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.016 A
子类别:DRAMs最大压摆率:1.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

M366S1623ETS-C1L 数据手册

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M366S1623ETS  
PC133/PC100 Unbuffered DIMM  
M366S1623ETS- C7A/C75/C1H/C1L  
• Organization : 16Mx64  
• Composition : 8Mx8 *16  
• Used component part # : K4S640832E-TC75/TC1H/TC1L  
• # of rows in module : 2 rows  
• # of banks in component : 4 banks  
• Feature : 1,375mil height & double sided component  
• Refresh : 4K/64ms  
Contents ;  
Function Supported  
-75 -1H  
128bytes  
Hex value  
Byte #  
Function Described  
Note  
-7A  
-1L  
-7A  
-75  
-1H  
-1L  
0
1
# of bytes written into serial memory at module manufacturer  
Total # of bytes of SPD memory device  
Fundamental memory type  
80h  
08h  
04h  
0Ch  
09h  
02h  
40h  
00h  
01h  
256bytes (2K-bit)  
2
SDRAM  
3
# of row address on this assembly  
12  
9
1
1
4
# of column address on this assembly  
5
# of module rows on this assembly  
Data width of this assembly  
2 rows  
64 bits  
-
6
7
...... Data width of this assembly  
8
Voltage interface standard of this assembly  
SDRAM cycle time @CAS latency of 3  
SDRAM access time from clock @CAS latency of 3  
DIMM configuration type  
LVTTL  
9
7.5ns 7.5ns  
5.4ns 5.4ns  
10ns  
6ns  
10ns  
6ns  
75h  
54h  
75h  
54h  
A0h  
60h  
A0h  
60h  
2
2
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Non parity  
00h  
80h  
08h  
00h  
01h  
8Fh  
04h  
Refresh rate & type  
15.625us, support self refresh  
Primary SDRAM width  
x8  
None  
Error checking SDRAM width  
Minimum clock delay for back-to-back random column address  
SDRAM device attributes : Burst lengths supported  
tCCD = 1CLK  
1, 2, 4, 8 & full page  
4 banks  
SDRAM device attributes : # of banks on SDRAM device  
SDRAM device attributes : CAS latency  
2 & 3  
3
2 & 3 2 & 3  
0 CLK  
0 CLK  
06h  
04h  
06h  
06h  
SDRAM device attributes : CS latency  
01h  
01h  
SDRAM device attributes : Write latency  
Non-buffered, non-registered  
& redundant addressing  
21  
SDRAM module attributes  
00h  
+/- 10% voltage tolerance,  
Burst Read Single bit Write  
precharge all, auto precharge  
22  
SDRAM device attributes : General  
0Eh  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
SDRAM cycle time @CAS latency of 2  
SDRAM access time from clock@CAS latency of 2  
SDRAM cycle time @CAS latency of 1  
SDRAM access time from clock@CAS latency of 1  
Minimum row precharge time (=tRP)  
10ns  
6ns  
-
-
10ns  
6ns  
12ns  
7ns  
A0h  
60h  
00h  
00h  
A0h  
60h  
C0h  
70h  
2
2
-
-
00h  
00h  
20ns  
15ns  
20ns  
45ns  
20ns  
15ns  
20ns  
45ns  
20ns  
20ns  
20ns  
50ns  
20ns  
20ns  
20ns  
50ns  
14h  
0Fh  
14h  
2Dh  
14h  
0Fh  
14h  
2Dh  
14h  
14h  
14h  
32h  
14h  
14h  
14h  
32h  
Minimum row active to row active delay (tRRD)  
Minimum RAS to CAS delay (=tRCD)  
Minimum activate precharge time (=tRAS)  
10h  
Module row density  
2 rows of 64MB  
Command and address signal input setup time  
Command and address signal input hold time  
Data signal input setup time  
1.5ns 1.5ns  
0.8ns 0.8ns  
1.5ns 1.5ns  
2ns  
1ns  
2ns  
2ns  
1ns  
2ns  
15h  
08h  
15h  
15h  
08h  
15h  
20h  
10h  
20h  
20h  
10h  
20h  
Rev. 0.2 Sept. 2001  

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