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M300LFXIT PDF预览

M300LFXIT

更新时间: 2024-11-08 21:03:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟外围集成电路晶体
页数 文件大小 规格书
17页 475K
描述
Clock Generator, 50MHz, CMOS, 3 X 3 MM, LEAD FREE, MO-220, QFN-24

M300LFXIT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:VQCCN,
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.78JESD-30 代码:S-XQCC-N16
JESD-609代码:e4长度:3 mm
湿度敏感等级:3端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:50 MHz封装主体材料:UNSPECIFIED
封装代码:VQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):260
主时钟/晶体标称频率:48 MHz认证状态:Not Qualified
座面最大高度:0.6 mm最大供电电压:1.95 V
最小供电电压:1.65 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

M300LFXIT 数据手册

 浏览型号M300LFXIT的Datasheet PDF文件第2页浏览型号M300LFXIT的Datasheet PDF文件第3页浏览型号M300LFXIT的Datasheet PDF文件第4页浏览型号M300LFXIT的Datasheet PDF文件第5页浏览型号M300LFXIT的Datasheet PDF文件第6页浏览型号M300LFXIT的Datasheet PDF文件第7页 
MoBL® Clock  
M300/M600  
Three-PLL Programmable Clock Generator  
for Portable Applications  
Three-PLL Programmable Clock Generator for Portable Applications  
Features  
Benefits  
Device Operating Voltage Options:  
MoBL Clock M300 Family: 1.8 V  
Suitable for cell phone, portable, and consumer electronics  
applications  
MoBL Clock M600 Family: 2.5 V, 3.0 V, or 3.3 V  
Multiple high-performance PLLs allow synthesis of unrelated  
frequencies  
Selectable clock output voltages for both MoBL Clock M300  
and M600:  
1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V  
Application compatibility in multiple output voltage levels  
Optional Spread Spectrum capable PLLs with Lexmark or  
Fully integrated ultra low power phase-locked loops (PLLs)  
Input reference clock frequency range: 1–48 MHz  
Output clock frequency range: 3–50 MHz  
Three I2C™ programmable output clocks  
Programmable output drive strengths  
150 ps typical cycle-to-cycle jitter  
Linear profile for maximum EMI reduction  
PLLs can be programmed for system frequency margin tests  
Meets critical timing requirements in complex system designs  
Individually enable or disable each output using I2C  
Ease of output clock selection using programmable crossbar  
switches  
Optional Spread Spectrum for EMI reduction  
16-pin (3 × 3 × 0.6 mm) QFN Package  
Industrial temperature range  
Logic Block Diagram  
VDD_CLK1  
VDD_CLK2  
VDD_CLK3  
EXCLKIN  
REF SEL  
CLK1  
CLK2  
Output  
Dividers  
and  
Crossbar  
Switch  
PLL1  
MUX  
and  
Control  
PLL2  
(SS)  
Drive  
Logic  
Strength  
Control  
PLL3  
(SS)  
CLK3  
SCL  
I2C  
SDA  
PD#/OE  
Cypress Semiconductor Corporation  
Document Number: 001-12946 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 7, 2010  
[+] Feedback  

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