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M2S12D30TP-10L PDF预览

M2S12D30TP-10L

更新时间: 2024-11-30 22:08:23
品牌 Logo 应用领域
三菱 - MITSUBISHI 内存集成电路光电二极管动态存储器双倍数据速率时钟
页数 文件大小 规格书
38页 752K
描述
512M Double Data Rate Synchronous DRAM

M2S12D30TP-10L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:SOP, TSSOP66,.46
针数:66Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.92Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:0.8 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):125 MHz
I/O 类型:COMMON交错的突发长度:2,4,8
JESD-30 代码:R-PDSO-G66JESD-609代码:e0
内存密度:536870912 bit内存集成电路类型:DDR DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:66
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP66,.46
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES连续突发长度:2,4,8
最大待机电流:0.006 A子类别:DRAMs
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

M2S12D30TP-10L 数据手册

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DDR SDRAM (Rev.1.1)  
MITSUBISHI LSIs  
MITSUBISHI  
ELECTRIC  
M2S12D20/ 30TP -75, -75L, -10, -10L  
Feb. '02  
512M Double Data Rate Synchronous DRAM  
DESCRIPTION  
M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit,  
M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit,  
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are  
referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and  
output data and data strobe are referenced on both edges of CLK. The M2S12D20/30TP achieve  
very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.  
FEATURES  
- Vdd=Vddq=2.5V+0.2V  
- Double data rate architecture; two data transfers per clock cycle  
- Bidirectional, data strobe (DQS) is transmitted/received with data  
- Differential clock inputs (CLK and /CLK)  
- DLL aligns DQ and DQS transitions  
- Commands are entered on each positive CLK edge;  
- data and data mask are referenced to both edges of DQS  
- 4 bank operations are controlled by BA0, BA1 (Bank Address)  
- /CAS latency- 2.0/2.5 (programmable)  
- Burst length- 2/4/8 (programmable)  
- Burst type- sequential / interleave (programmable)  
- Auto precharge / All bank precharge is controlled by A10  
- 8192 refresh cycles /64ms (4 banks concurrent refresh)  
- Auto refresh and Self refresh  
- Row address A0-12 / Column address A0-9,11-12(x4)/ A0-9,11(x8)  
SSTL_2 Interface  
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)  
- JEDEC standard  
- Low Power for the Self Refresh Current ICC6 :4mA (-75L,-10L)  
Operating Frequencies  
Speed Grade  
Clock Rate  
CL=2.5 *  
CL=2 *  
100MHz  
100MHz  
-75 / -75L  
-10 / -10L  
133MHz  
125MHz  
* CL = CAS(Read) Latency  
Contents are subject to change without notice.  
-1-  
MITSUBISHI ELECTRIC  

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