Datasheet > 存储 > 闪存> M29F002NT-70XK6TR

M29F002NT-70XK6TR

更新时间： 2024-01-30 22:30:50

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		闪存存储内存集成电路
页数	文件大小	规格书
29页	199K
描述
2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory

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技术参数
数据手册

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M29F002NT-70XK6TR 技术参数

生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	QCCJ,	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.11
最长访问时间：	70 ns	其他特性：	20 YEARS DATA RETENTION; 100000 PROGRAM/ERASE CYCLES
启动块：	TOP	数据保留时间-最小值：	20
JESD-30 代码：	R-PQCC-J32	长度：	13.995 mm
内存密度：	2097152 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
端子数量：	32	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
编程电压：	5 V	认证状态：	Not Qualified
座面最大高度：	3.56 mm	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
类型：	NOR TYPE	宽度：	11.455 mm
Base Number Matches：	1

M29F002NT-70XK6TR 数据手册

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M29F002T, M29F002NT, M29F002B

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

–40 to 125

–50 to 125

–65 to 150

–0.6 to 7

Unit

°C

Ambient Operating Temperature ⁽³⁾

Temperature Under Bias

Storage Temperature

T_BIAS

T_STG

(2)

V_IO

Input or Output Voltages

Supply Voltage

V_CC

–0.6 to 7

(2)

V_{(A9, E, G, RPNC)}

A9, E, G, RPNC Voltage

–0.6 to 13.5

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltagemay undershoot to –2V during transitionand for less than 20ns.

3. Depends on range.

Organisation

from or program to any block not being ersased,

and then resumed.Block protection providesaddi-

tional data security. Each block can be separately

protectedor unprotectedagainstProgramor Erase

on programming equipment. All previously pro-

tectedblockscan be temporarilyunprotectedin the

application.

The M29F002 is organised as 256K x 8. Memory

control is provided by Chip Enable E, Output En-

able G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RPNC

(NOTavailable on M29F002NT) tri-level input pro-

videsa hardwareresetwhenpulledLow,andwhen

held High (at V_ID) temporarily unprotects blocks

previously protected allowing them to be progra-

med and erased. Erase and Program operations

are controlled by an internal Program/Erase Con-

troller(P/E.C.).StatusRegisterdataoutputon DQ7

provides a Data Pollingsignal, and DQ6 and DQ2

provide Toggle signals to indicate the state of the

P/E.C operations.

Bus Operations

The following operations can be performed using

theappropriatebus cycles:Read(Array, Electronic

Signature, Block Protection Status), Write com-

mand, Output Disable, Standby,Reset, Block Pro-

tection, Unprotection, Protection Verify,

Unprotection Verify and Block Temporary Unpro-

tection. See Tables4 and 5.

Memory Blocks

Command Interface

The devices feature asymmetricallyblocked archi-

tecture providing system memory integration. The

M29F002has an arrayof 7blocks, one Boot Block

of 16 KBytes, two Parameter Blocks of 8 KBytes,

oneMainBlockof 32KBytesandthreeMainBlocks

of 64 KBytes.

Instructions, made up of commands written in cy-

cles, can be given to the Program/EraseController

through a Command Interface (C.I.). For added

data protection,program or erase execution starts

after4 or6 cycles.The first,second,fourthand fifth

cycles are used to input Coded cycles to the C.I.

This Coded sequence is the same for all Pro-

gram/Erase Controller instructions. The ’Com-

mand’ itself and its confirmation, when applicable,

are given on the third, fourth or sixth cycles. Any

incorrect command or any improper command se-

quencewill reset the device to Read Array mode.

Thememory map is shownin Figure3. Eachblock

can be erased separately, any combination of

blockscan be specifiedfor multi-blockerase or the

entire chip may be erased. The Erase operations

aremanagedautomaticallybythe P/E.C.Theblock

eraseoperationcan be suspendedin orderto read

3/29

1 234 5 6 7...29

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