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M27W201-80F6TR PDF预览

M27W201-80F6TR

更新时间: 2024-01-28 11:52:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路可编程只读存储器OTP只读存储器电动程控只读存储器
页数 文件大小 规格书
16页 173K
描述
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM

M27W201-80F6TR 技术参数

生命周期:Obsolete包装说明:WDIP,
Reach Compliance Code:unknown风险等级:5.82
Is Samacsys:N最长访问时间:80 ns
JESD-30 代码:R-CDIP-T32长度:41.885 mm
内存密度:2097152 bit内存集成电路类型:OTP ROM
内存宽度:8功能数量:1
端子数量:32字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX8封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:WDIP封装形状:RECTANGULAR
封装形式:IN-LINE, WINDOW并行/串行:PARALLEL
座面最大高度:5.72 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:15.24 mm
Base Number Matches:1

M27W201-80F6TR 数据手册

 浏览型号M27W201-80F6TR的Datasheet PDF文件第2页浏览型号M27W201-80F6TR的Datasheet PDF文件第3页浏览型号M27W201-80F6TR的Datasheet PDF文件第4页浏览型号M27W201-80F6TR的Datasheet PDF文件第6页浏览型号M27W201-80F6TR的Datasheet PDF文件第7页浏览型号M27W201-80F6TR的Datasheet PDF文件第8页 
M27W201  
(1)  
Table 7. Read Mode DC Characteristics  
(T = –40 to 85 °C; V = 2.7V to 3.6V; V = V  
)
A
CC  
PP  
CC  
Symbol  
Parameter  
Test Condition  
Min  
Max  
Unit  
µA  
I
LI  
Input Leakage Current  
Output Leakage Current  
±10  
±10  
0V V V  
IN  
CC  
I
0V V V  
OUT CC  
µA  
LO  
E = V , G = V ,  
IL  
IL  
I
I
= 0mA, f = 5MHz  
OUT  
Supply Current  
15  
mA  
CC  
V
CC  
≤ 3.6V  
I
I
1
2
E = V  
IH  
Supply Current (Standby) TTL  
Supply Current (Standby) CMOS  
1
mA  
µA  
CC  
CC  
I
E > V – 0.2V  
CC  
15  
V
≤ 3.6V  
CC  
V
= V  
Program Current  
10  
µA  
V
PP  
PP  
CC  
V
0.2 V  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage TTL  
–0.6  
IL  
(2)  
CC  
0.7 V  
V
+ 0.5  
CC  
V
V
CC  
IH  
V
I
= 2.1mA  
0.4  
V
OL  
OL  
V
I
= –400µA  
2.4  
V
OH  
OH  
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .  
PP  
CC  
PP  
2. Maximum DC voltage on Output is V +0.5V.  
CC  
Two Line Output Control  
System Considerations  
Because EPROMs are usually used in larger  
memory arrays, this product features a 2 line con-  
trol function which accommodates the use of mul-  
tiple memory connection. The two line control  
function allows:  
a. the lowest possible memory power dissipation,  
b. complete assurance that output bus contention  
will not occur.  
For the most efficient use of these two control  
lines, E should be decoded and used as the prima-  
ry device selecting function, while G should be  
made a common connection to all devices in the  
array and connected to the READ line from the  
system control bus. This ensures that all deselect-  
ed memory devices are in their low power standby  
mode and that the output pins are only active  
when data is required from a particular memory  
device.  
The power switching characteristics of Advanced  
CMOS EPROMs require careful decoupling of the  
devices. The supply current, I , has three seg-  
CC  
ments that are of interest to the system designer:  
the standby current level, the active current level,  
and transient current peaks that are produced by  
the falling and rising edges of E. The magnitude of  
the transient current peaks is dependent on the  
capacitive and inductive loading of the device at  
the output.  
The associated transient voltage peaks can be  
suppressed by complying with the two line output  
control and by properly selected decoupling ca-  
pacitors. It is recommended that a 0.1µF ceramic  
capacitor be used on every device between V  
CC  
and V . This should be a high frequency capaci-  
SS  
tor of low inherent inductance and should be  
placed as close to the device as possible. In addi-  
tion, a 4.7µF bulk electrolytic capacitor should be  
used between V and V for every eight devic-  
CC  
SS  
es. The bulk capacitor should be located near the  
power supply connection point. The purpose of the  
bulk capacitor is to overcome the voltage drop  
caused by the inductive effects of PCB traces.  
5/16  

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