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M27C405-100B6 PDF预览

M27C405-100B6

更新时间： 2023-01-02 16:52:29
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器光电二极管
页数 文件大小 规格书
14页 147K
描述
512KX8 OTPROM, 100ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32

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M27C405-100B6 数据手册

 浏览型号M27C405-100B6的Datasheet PDF文件第3页浏览型号M27C405-100B6的Datasheet PDF文件第4页浏览型号M27C405-100B6的Datasheet PDF文件第5页浏览型号M27C405-100B6的Datasheet PDF文件第7页浏览型号M27C405-100B6的Datasheet PDF文件第8页浏览型号M27C405-100B6的Datasheet PDF文件第9页 
M27C405  
(1)  
Table 8B. Read Mode AC Characteristics  
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 10%; V = V  
)
A
CC  
PP  
CC  
M27C405  
-120  
Symbol  
Alt  
Parameter  
Test Condition  
-100  
-150  
Unit  
Min Max Min Max Min Max  
t
t
E = V , G = V  
Address Valid to Output Valid  
Chip Enable Low to Output Valid  
Output Enable Low to Output Valid  
100  
100  
50  
120  
120  
60  
150 ns  
150 ns  
AVQV  
ACC  
IL  
IL  
t
t
G = V  
IL  
ELQV  
CE  
t
t
E = V  
IL  
60  
50  
50  
ns  
ns  
ns  
GLQV  
OE  
(2)  
t
t
G = V  
Chip Enable High to Output Hi-Z  
Output Enable High to Output Hi-Z  
0
0
30  
30  
0
0
40  
40  
0
0
t
DF  
DF  
IL  
EHQZ  
(2)  
E = V  
t
IL  
GHQZ  
Address Transition to Output  
Transition  
t
t
E = V , G = V  
IL IL  
0
0
0
ns  
AXQX  
OH  
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .  
PP  
CC  
PP  
2. Sampled only, not 100% tested  
Figure 5. Read Mode AC Waveforms  
VALID  
tGLQV  
VALID  
A0-A18  
tAVQV  
tAXQX  
E
tEHQZ  
tGHQZ  
G
tELQV  
Hi-Z  
Q0-Q7  
AI00724B  
System Considerations  
The power switching characteristics of Advanced  
CMOS EPROMs require careful decoupling of the  
output control and by properly selected decoupling  
capacitors. It is recommended that a 0.1µF ceram-  
ic capacitor be used on every device between V  
CC  
and V . This should be a high frequency capaci-  
SS  
devices. The supply current, I , has three seg-  
CC  
tor of low inherent inductance and should be  
placed as close to the device as possible. In addi-  
tion, a 4.7µF bulk electrolytic capacitor should be  
ments that are of interest to the system designer:  
the standby current level, the active current level,  
and transient current peaks that are produced by  
the falling and rising edges of E. The magnitude of  
the transient current peaks is dependent on the  
capacitive and inductive loading of the device at  
the output. The associated transient voltage peaks  
can be suppressed by complying with the two line  
used between V and V for every eight devic-  
CC  
SS  
es. The bulk capacitor should be located near the  
power supply connection point. The purpose of the  
bulk capacitor is to overcome the voltage drop  
caused by the inductive effects of PCB traces.  
6/14  
1...3456789...14

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