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M27C405-100B6 PDF预览

M27C405-100B6

更新时间： 2023-01-02 16:52:29
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器光电二极管
页数 文件大小 规格书
14页 147K
描述
512KX8 OTPROM, 100ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32

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M27C405-100B6 数据手册

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M27C405  
(1)  
Table 7. Read Mode DC Characteristics  
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 10%; V = V  
)
A
CC  
PP  
CC  
Symbol  
Parameter  
Input Leakage Current  
Output Leakage Current  
Test Condition  
Min  
Max  
±10  
±10  
Unit  
µA  
I
0V ≤ V ≤ V  
LI  
IN  
CC  
I
LO  
0V ≤ V  
≤ V  
OUT CC  
µA  
E = V , G = V ,  
IL  
IL  
I
Supply Current  
30  
mA  
CC  
I
= 0mA, f = 5MHz  
OUT  
I
E = V  
Supply Current (Standby) TTL  
Supply Current (Standby) CMOS  
Program Current  
1
mA  
µA  
µA  
V
CC1  
IH  
I
E > V  
– 0.2V  
CC  
100  
10  
CC2  
I
PP  
V
= V  
PP CC  
V
Input Low Voltage  
–0.3  
2
0.8  
IL  
(2)  
V
+ 1  
Input High Voltage  
V
V
V
V
V
CC  
IH  
V
I
= 2.1mA  
= –400µA  
= –100µA  
Output Low Voltage  
0.4  
OL  
OL  
I
Output High Voltage TTL  
Output High Voltage CMOS  
2.4  
OH  
OH  
V
OH  
I
V
– 0.7V  
CC  
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .  
PP  
CC  
PP  
2. Maximum DC voltage on Output is V +0.5V.  
CC  
(1)  
Table 8A. Read Mode AC Characteristics  
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 10%; V = V  
)
A
CC  
PP  
CC  
M27C405  
-80  
(3)  
Symbol  
Alt  
Parameter  
Test Condition  
-90  
Unit  
-70  
Min Max Min Max Min Max  
t
t
E = V , G = V  
Address Valid to Output Valid  
70  
70  
35  
30  
80  
80  
40  
30  
90  
90  
40  
30  
ns  
ns  
ns  
ns  
AVQV  
ACC  
IL  
IL  
t
t
G = V  
IL  
Chip Enable Low to Output Valid  
Output Enable Low to Output Valid  
Chip Enable High to Output Hi-Z  
ELQV  
CE  
t
t
E = V  
IL  
GLQV  
OE  
(2)  
t
t
G = V  
0
0
0
0
0
0
t
DF  
DF  
IL  
EHQZ  
GHQZ  
t
(2)  
E = V  
Output Enable High to Output Hi-Z  
30  
30  
30  
ns  
ns  
t
IL  
Address Transition to Output  
Transition  
t
E = V , G = V  
IL IL  
0
0
0
AXQX  
OH  
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .  
PP  
CC  
PP  
2. Sampled only, not 100% tested.  
3. Speed obtained with High Speed AC Measurement conditions.  
Two Line Output Control  
For the most efficient use of these two control  
lines, E should be decoded and used as the prima-  
ry device selecting function, while G should be  
made a common connection to all devices in the  
array and connected to the READ line from the  
system control bus. This ensures that all deselect-  
ed memory devices are in their low power standby  
mode and that the output pins are only active  
when data is required from a particular memory  
device.  
Because OTP EPROMs are usually used in larger  
memory arrays, this product features a 2 line con-  
trol function which accommodates the use of mul-  
tiple memory connection. The two line control  
function allows:  
a. the lowest possible memory power dissipation,  
b. complete assurance that output bus contention  
will not occur.  
5/14  
12345678...14

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