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M2006-02A-666.514T PDF预览

M2006-02A-666.514T

更新时间: 2024-12-02 05:05:39
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艾迪悌 - IDT /
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8页 408K
描述
CLCC-36, Reel

M2006-02A-666.514T 数据手册

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P r o d u c t D a t a S h e e t  
Integrated  
Circuit  
Systems, Inc.  
M2006-02A  
VCSO BASED FEC CLOCK PLL  
GENERAL DESCRIPTION  
PIN ASSIGNMENT (9 x 9 mm SMT)  
The M2006-02A is a VCSO (Voltage Controlled SAW  
Oscillator) based clock generator  
PLL designed for clock frequency  
translation and jitter attenuation.  
The device supports both forward  
and inverse FEC (Forward Error  
Correction) clock multiplication  
FIN_SEL0  
FEC_SEL0  
FEC_SEL1  
FEC_SEL2  
FEC_SEL3  
VCC  
P0_SEL  
P1_SEL  
nFOUT0  
FOUT0  
GND  
nFOUT1  
FOUT1  
VCC  
28  
29  
30  
31  
18  
17  
16  
15  
14  
13  
12  
11  
10  
ratios. Multiplication ratios are  
A
M2006-02  
pin-selected from pre-programming look-up tables.  
32  
33  
34  
35  
36  
( T o p V i e w )  
DNC  
DNC  
FEATURES  
Reduced intrinsic output jitter and improved power  
supply noise rejection compared to M2006-02  
DNC  
GND  
Low phase jitter of 0.25 ps rms typical  
(12kHz to 20MHz or 50kHz to 80MHz)  
Pin-selectable PLL divider ratios support forward and  
inverse FEC ratio translation, including:  
• 255/238 (OTU1) Mapping and 238/255 De-mapping  
• 255/237 (OTU2) Mapping and 237/255 De-mapping  
• 255/236 (OTU3) Mapping and 236/255 De-mapping  
Figure 1: Pin Assignment  
Example I/O Clock Combinations  
Using M2006-02A-622.0800  
Input reference and VCSO frequencies up to 700MHz,  
supports loop timing modes  
(Specify VCSO frequency at time of order)  
PLL Ratio  
Input Clock (MHz) Output Clock (MHz)  
1/1  
622.08, 155.52,  
77.76, or 19.44  
Supports active switching between inverse-FEC and  
non-FEC clock ratios (same VCSO center frequency)  
622.08  
or  
237/255  
669.3266, 167.3316,  
155.52  
Ideal for complex ratio FEC ratio translation and  
for use with an unstable reference (i.e., similar to the  
M2006-12A - and pin-compatible - but without the  
Hitless Switching and Phase Build-out functions)  
(inverse FEC) 83.6658, or 20.9165  
Table 1: Example I/O Clock Combinations Using M2006-02A-622.0800  
Using M2006-02A-669.3266  
Single 3.3V power supply  
PLL Ratio  
Input Clock (MHz) Output Clock (MHz)  
Small 9 x 9 mm SMT (surface mount) package  
237/255  
(FEC rate)  
622.08, 155.52,  
77.76, or 19.44  
669.3266  
or  
1/1  
669.3266, 167.3316,  
167.3316  
83.6658, or 20.9165  
Table 2: Example I/O Clock Combinations Using M2006-02A-669.3266  
SIMPLIFIED BLOCK DIAGRAM  
Loop  
Filter  
M2006-02A  
DIF_REF0  
0
nDIF_REF0  
Rfec Div  
DIF_REF1  
1
FOUT0  
P0 Div  
VCSO  
(1 or 4)  
nFOUT0  
nDIF_REF1  
Mfin Div  
Mfec Div  
(1, 4, 8, or 32)  
REF_SEL  
4
2
Mfec / Rfec  
Divider LUT  
FOUT1  
FEC_SEL3:0  
FIN_SEL1:0  
P1 Div  
(1 or 4)  
nFOUT1  
Mfin Divider  
LUT  
P0_SEL  
Figure 2: Simplified Block Diagram  
P1_SEL  
M2006-02A Datasheet Rev 1.0  
Revised 28Jul2004  
M2006-02A VCSO Based FEC Clock PLL  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  

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