Datasheet > M2006-01-672.1600LF

M2006-01-672.1600LF

更新时间： 2024-11-30 21:13:47

品牌	Logo	应用领域
艾迪悌 - IDT		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
10页	911K
描述
Support Circuit, 1-Func, 9 X 9 MM, SMT-36

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M2006-01-672.1600LF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	QFN
包装说明：	QCCN,	针数：	36
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.42	JESD-30 代码：	S-XQCC-N36
JESD-609代码：	e3	长度：	9 mm
功能数量：	1	端子数量：	36
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	UNSPECIFIED	封装代码：	QCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	2.8 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.635 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	9 mm	Base Number Matches：	1

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M2006-01

Micro Networks

An Integrated Circuit Systems Company

Preliminary Specifications

M2 0 0 6 -0 1

Frequency Synthesizer

DESCRIPTION

The M2006-01 integrates a high performance Phase Locked

Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO)

to provide a low jitter Frequency Synthesizer in a 9mm x

9mm surface mount package.

The internal high “Q” SAW filter provides low jitter signal

performance and determines the output frequency of the

VCSO.

Selecting between two differential LVPECL clocks or one

single-ended LVCMOS / LVTTL clock provides the input

reference signal to the Frequency Translator. The maximum

input frequency is 700MHz.

The M2006-01 will default to a multiplying factor of 32 on

power-up. The multiplying factor can be changed by serially

programming the input and feedback dividers via the

configuration logic.

FEATURES

A differential LVPECL signal provides the output clock for

the device. A second differential output which can be

programmed to divide the output frequency by a factor of 4

is also available. The output frequency can be momentarily

increased or decreased to add or subtract one net output

clock cycle by asserting the ADD_CLK or DROP_CLK

inputs, respectively.

Output Clock Frequency up to 700MHz

Intrinsic Jitter <1ps rms (12kHz - 50MHz)

Automatic Phase Slope Limiting

Dual Differential Inputs

An external loop filter sets the PLL bandwidth which can be

optimized to provide jitter attenuation of the input reference

clock. A phase slope limiting feature, which reduces phase

build-out in order to meet GR-253 MTIE upon an input

transient, can be manually selected by asserting the PSL

input. The phase slope limiting feature is automatically

activated whenever a new input reference clock is selected.

Input Compatible with LVPECL, LVDS,

HSTL, SSTL, etc.

Triple Input MUX

Configurable Input and Feedback Dividers

Tunable Loop Filter Response

Two Differential LVPECL outputs

Single 3.3V Supply

The frequency agility, bandwidth control, and phase slope

limiting features make the M2006-01 ideal for use as a clock

jitter attenuator, frequency translator, and clock frequency

generator in OC-3 through OC-192 applications.

Small 9mm x 9mm SMT Package

ABSOLUTE MAX RATINGS

Inputs, V :

................................................. -0.5 to V_CC+0.5V

APPLICATIONS

Output, V_O: ................................................. -0.5 to V_CC+0.5V

Supply Voltage, V_CC: ......................................................... 4.6 V

Storage Temperature, T_STO:............................ -45°C to +100°C

SONET / SDH / 10GbE System

Synchronization

Add / Drop Muxes, Access and Edge

Switches

Stresses beyond those listed under Absolute Maximum Ratings may cause

permanent damage to the device. These ratings are stress specifications only.

Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect product reliability.

Line Card System Clock Cleaner /

Translator

Optical Module Clock Cleaner / Translator

ISO 9001

Registered

Micro Networks

324 Clark Street

Worcester, MA 01606

tel: 508-852-5400

fax: 508-852-8456

www.micronetworks.com

12 3 4 5 6 7...10

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与M2006-01-672.1600LF相关器件

型号	品牌	获取价格	描述	数据表
M2006-01-690.5692	IDT	获取价格	Support Circuit, 1-Func, 9 X 9 MM, SMT-36
M2006-01-690.5692LF	IDT	获取价格	Support Circuit, 1-Func, 9 X 9 MM, SMT-36
M2006-01-693.4830	IDT	获取价格	Support Circuit, 1-Func, 9 X 9 MM, SMT-36
M2006-01-693.4830LF	IDT	获取价格	Support Circuit, 1-Func, 9 X 9 MM, SMT-36
M2006-02	ICSI	获取价格	VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION
M2006-02	ICSI	获取价格	VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION
M2006-02-625.0000	IDT	获取价格	CLCC-36, Tube
M2006-02-625.0000LF	IDT	获取价格	PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,
M2006-02-625.0000T	IDT	获取价格	CLCC-36, Reel
M2006-02-627.3296LF	IDT	获取价格	PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,

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