Datasheet > M1AFS1500-FG484K

M1AFS1500-FG484K

更新时间： 2024-11-10 15:46:23

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
331页	18440K
描述
Field Programmable Gate Array, 350MHz, 38400-Cell, CMOS, PBGA484,

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M1AFS1500-FG484K 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	BGA, BGA484,22X22,40	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.85
最大时钟频率：	350 MHz	JESD-30 代码：	S-PBGA-B484
JESD-609代码：	e0	湿度敏感等级：	3
输入次数：	223	逻辑单元数量：	38400
输出次数：	223	端子数量：	484
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA484,22X22,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	225
电源：	1.5,3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	子类别：	Field Programmable Gate Arrays
表面贴装：	YES	技术：	CMOS
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	Base Number Matches：	1

M1AFS1500-FG484K 数据手册

Revision 6

Fusion Family of Mixed Signal FPGAs

In-System Programming (ISP) and Security

Features and Benefits

•

ISP with 128-Bit AES via JTAG

High-Performance Reprogrammable Flash

Technology

FlashLock Designed to Protect FPGA Contents

Advanced Digital I/O

•

Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS

Process

•

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

•

Nonvolatile, Retains Program when Powered Off

Instant On Single-Chip Solution

350 MHz System Performance

Embedded Flash Memory

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS,

M-LVDS

•

User Flash Memory – 2 Mbits to 8 Mbits

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

1 Kbit of Additional FlashROM

– Built-In I/O Registers

– 700 Mbps DDR Operation

•

Hot-Swappable I/Os

•

Programmable Output Slew Rate, Drive Strength, and

Weak Pull-Up/Down Resistor

Integrated A/D Converter (ADC) and Analog I/O

•

Up to 12-Bit Resolution and up to 600 Ksps

Internal 2.56 V or External Reference Voltage

ADC: Up to 30 Scalable Analog Input Channels

High-Voltage Input Tolerance: –10.5 V to +12 V

Current Monitor and Temperature Monitor Blocks

Up to 10 MOSFET Gate Driver Outputs

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA, and 20 mA Drive

Strengths

•

Pin-Compatible Packages across the Fusion Family

SRAMs and FIFOs

•

Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2,

×4, ×9, and ×18 organizations available)

•

True Dual-Port SRAM (except ×18)

Programmable Embedded FIFO Control Logic

Soft ARM Cortex-M1 Fusion Devices (M1)

•

ARM Cortex-™M1–Enabled

•

ADC Accuracy is Better than 1%

Pigeon Point ATCA IP Support (P1)

On-Chip Clocking Support

•

Targeted to Pigeon Point

Reference (BMR) Starter Kits

Board Management

•

Internal 100 MHz RC Oscillator (accurate to 1%)

Crystal Oscillator Support (32 KHz to 20 MHz)

Programmable Real-Time Counter (RTC)

6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated

PLLs

•

Designed in Partnership with Pigeon Point Systems

ARM Cortex-M1 Enabled

MicroBlade Advanced Mezzanine Card Support (U1)

•

Targeted to Advanced Mezzanine Card (AdvancedMC™

Designs)

– Phase Shift, Multiply/Divide, and Delay Capabilities

– Frequency: Input 1.5–350 MHz, Output 0.75–350

MHz

•

Designed in Partnership with MicroBlade

8051-Based Module Management Controller (MMC)

Low Power Consumption

•

Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

Sleep and Standby Low-Power Modes

Table 1 • Fusion Family

Fusion Devices

AFS090

AFS250

AFS600

AFS1500

ARM Cortex-M1 Devices

M1AFS250

M1AFS600

M1AFS1500

Pigeon Point Devices

MicroBlade Devices

P1AFS600

P1AFS1500

U1AFS250

U1AFS600

U1AFS1500

System Gates

90,000

2,304

Yes

250,000

600,000

13,824

Yes

1,500,000

38,400

Yes

Tiles (D-flip-flops)

Secure (AES) ISP

PLLs

6,144

Yes

General

Information

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

FlashROM Bits

1,024

Memory

1,024

RAM Blocks (4,608 bits)

RAM kbits

108

270

Analog Quads

Analog Input Channels

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

Analog and I/Os

114

172

252

Note: *Refer to the Cortex-M1 product brief for more information.

March 2014

12 3 4 5 6 7...331

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与M1AFS1500-FG484K相关器件

型号	品牌	获取价格	描述	数据表
M1AFS1500-FG484PP	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
M1AFS1500-FG484Y	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
M1AFS1500-FG484YES	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
M1AFS1500-FG484YI	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
M1AFS1500-FG484YK	MICROSEMI	获取价格	Field Programmable Gate Array,
M1AFS1500-FG484YPP	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
M1AFS1500-FG676	MICROSEMI	获取价格	Field Programmable Gate Array, 38400 CLBs, 1500000 Gates, CMOS, PBGA676, 1 MM PITCH, FBGA-
M1AFS1500-FG676Y	MICROSEMI	获取价格	Field Programmable Gate Array,
M1AFS1500-FG676YI	MICROSEMI	获取价格	Field Programmable Gate Array,
M1AFS1500-FGG256	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs

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