5秒后页面跳转
捷配首页

Datasheet > M1AFS1500-1FGG484K
M1AFS1500-1FGG484K PDF预览

M1AFS1500-1FGG484K

更新时间： 2024-11-09 03:07:35
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
294页 16781K
描述
FPGA

阅读下载

中文翻译

获取价格

M1AFS1500-1FGG484K 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：BGA, BGA484,22X22,40Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.82
最大时钟频率：350 MHzJESD-30 代码：S-PBGA-B484
JESD-609代码：e1湿度敏感等级：3
输入次数：223逻辑单元数量：38400
输出次数：223端子数量：484
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA484,22X22,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：250
电源：1.5,3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified子类别：Field Programmable Gate Arrays
表面贴装：YES技术：CMOS
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30

M1AFS1500-1FGG484K 数据手册

 浏览型号M1AFS1500-1FGG484K的Datasheet PDF文件第2页浏览型号M1AFS1500-1FGG484K的Datasheet PDF文件第3页浏览型号M1AFS1500-1FGG484K的Datasheet PDF文件第4页浏览型号M1AFS1500-1FGG484K的Datasheet PDF文件第5页浏览型号M1AFS1500-1FGG484K的Datasheet PDF文件第6页浏览型号M1AFS1500-1FGG484K的Datasheet PDF文件第7页 
Revision 2  
Extended Temperature Fusion Family of Mixed Signal FPGAs  
•
6 Clock Conditioning Circuits (CCCs) with 2 Integrated PLLs  
Features and Benefits  
–
–
Phase Shift, Multiply/Divide, and Delay Capabilities  
Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz  
Extended Temperature Tested  
•
Each Device Tested from –55°C to 100°C Junction Temperature  
Low Power Consumption  
•
•
High-Performance Reprogrammable Flash Technology  
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator  
Sleep and Standby Low-Power Modes  
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process  
Nonvolatile, Retains Program when Powered Off  
Instant On Single-Chip Solution  
In-System Programming (ISP) and Security  
•
•
ISP with 128-Bit AES via JTAG  
350 MHz System Performance  
FlashLock® Designed to Secure FPGA Contents  
Embedded Flash Memory  
Advanced Digital I/O  
•
User Flash Memory – 4 Mbits to 8 Mbits  
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS  
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and  
LVCMOS 2.5 V / 5.0 V Input  
–
–
Configurable 16- or 32-Bit Datapath  
10 ns Access in Read-Ahead Mode  
•
1 Kbit of Additional FlashROM  
Integrated A/D Converter (ADC) and Analog I/O  
•
•
•
•
•
•
Up to 12-Bit Resolution and Up to 600 Ksps  
Internal 2.56 V or External Reference Voltage  
ADC: 30 Scalable Analog Input Channels  
High-Voltage Input Tolerance: –10.5 V to +12 V  
Current Monitor† and Temperature Monitor Blocks  
Up to 10 MOSFET Gate Driver Outputs  
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS  
–
–
Built-In I/O Registers  
700 Mbps DDR Operation  
•
•
Hot-Swappable I/Os  
Programmable Output Slew Rate, Drive Strength, and Weak  
Pull-Up/Pull-Down Resistor  
•
Pin-Compatible Packages across the Fusion® Family  
–
–
P- and N-Channel Power MOSFET Support  
Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths  
SRAMs and FIFOs  
•
•
ADC Accuracy Is Better than 1%  
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9, and  
×18 organizations available)  
On-Chip Clocking Support  
•
•
•
Internal 100 MHz RC Oscillator (Accurate to 1%)  
Crystal Oscillator Support (32 KHz to 20 MHz)  
Programmable Real-Time Counter (RTC)  
•
•
True Dual-Port SRAM (except ×18)  
Programmable Embedded FIFO Control Logic  
Soft ARM® Cortex™- M1 Fusion Devices (M1)  
•
ARM Cortex-M1–Enabled  
Table 1 • Fusion Extended Temperature Devices  
Fusion Devices  
AFS600  
AFS1500  
*
ARM Cortex-M1 Devices  
M1AFS600  
M1AFS1500  
System Gates  
600,000  
13,824  
Yes  
2
1,500,000  
38,400  
Yes  
2
Tiles (D-flip-flops)  
General Information  
Secure (AES) ISP  
PLLs  
Globals  
18  
18  
Flash Memory Blocks (2 Mbits)  
Total Flash Memory Bits  
FlashROM Bits  
2
4
4M  
1,024  
24  
8M  
Memory  
1,024  
60  
RAM Blocks (4,608 bits)  
RAM kbits  
108  
10  
270  
10  
Analog Quads  
Analog Input Channels  
Gate Driver Outputs  
I/O Banks (+ JTAG)  
Maximum Digital I/Os  
Analog I/Os  
30  
30  
10  
10  
Analog and I/Os  
5
5
172  
40  
223  
40  
Note: *Refer to the Cortex-M1 product brief for more information.  
† Refer to Table 2 on page IV for details.  
January 2013  
I
© 2013 Microsemi Corporation  
1234567...294

中文翻译

下载PDF

与M1AFS1500-1FGG484K相关器件

型号 品牌 获取价格 描述 数据表
M1AFS1500-1FGG484PP MICROSEMI

获取价格

 		Fusion Family of Mixed Signal FPGAs
M1AFS1500-1FGG484Y MICROSEMI

获取价格

 		Fusion Family of Mixed Signal FPGAs
M1AFS1500-1FGG484YES MICROSEMI

获取价格

 		Fusion Family of Mixed Signal FPGAs
M1AFS1500-1FGG484YI MICROSEMI

获取价格

 		Fusion Family of Mixed Signal FPGAs
M1AFS1500-1FGG484YK MICROSEMI

获取价格

 		Field Programmable Gate Array,
M1AFS1500-1FGG484YPP MICROSEMI

获取价格

 		Fusion Family of Mixed Signal FPGAs
M1AFS1500-1FGG676Y MICROSEMI

获取价格

 		Field Programmable Gate Array,
M1AFS1500-1FGG676YI MICROSEMI

获取价格

 		Field Programmable Gate Array,
M1AFS1500-1PQ256 MICROSEMI

获取价格

 		Fusion Family of Mixed Signal FPGAs
M1AFS1500-1PQ256ES MICROSEMI

获取价格

 		Fusion Family of Mixed Signal FPGAs

与M1AFS1500-1FGG484K相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证