Datasheet > M1A3P400-1PQ208Y

M1A3P400-1PQ208Y

更新时间： 2024-11-12 13:35:15

品牌	Logo	应用领域
美高森美 - MICROSEMI		栅可编程逻辑
页数	文件大小	规格书
221页	6465K
描述
Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

M1A3P400-1PQ208Y 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.89
JESD-30 代码：	S-PQFP-G208	长度：	28 mm
可配置逻辑块数量：	9216	等效关口数量：	400000
端子数量：	208	最高工作温度：	85 °C
最低工作温度：		组织：	9216 CLBS, 400000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	座面最大高度：	4.1 mm
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	28 mm
Base Number Matches：	1

M1A3P400-1PQ208Y 数据手册

Revision 18

DS0097

ProASIC3 Flash Family FPGAs

with Optional Soft ARM Support

Advanced I/O

Features and Benefits

•

700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

High Capacity

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

•

15 K to 1 M System Gates

Up to 144 Kbits of True Dual-Port SRAM

Up to 300 User I/Os

•

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

Reprogrammable Flash Technology

†

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

2.5 V / 5.0 V Input

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and above)

•

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

•

I/O Registers on Input, Output, and Enable Paths

‡

Hot-Swappable and Cold Sparing I/Os

High Performance

†

Programmable Output Slew Rate and Drive Strength

•

350 MHz System Performance

Weak Pull-Up/-Down

†

3.3 V, 66 MHz 64-Bit PCI

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the ProASIC3 Family

In-System Programming (ISP) and Security

Clock Conditioning Circuit (CCC) and PLL^†

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM -enabled ProASIC 3 devices)

•

Six CCC Blocks, One with an Integrated PLL

Configurable Phase-Shift, Multiply/Divide, Delay Capabilities

and External Feedback

†

via JTAG (IEEE 1532–compliant)

•

FlashLock to Secure FPGA Contents

Low Power

•

Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory^†

•

Core Voltage for Low Power

Support for 1.5 V-Only Systems

Low-Impedance Flash Switches

•

1 Kbit of FlashROM User Nonvolatile Memory

SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

†

High-Performance Routing Hierarchy

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

•

Segmented, Hierarchical Routing and Clock Structure

•

True Dual-Port SRAM (except ×18)

ARM Processor Support in ProASIC3 FPGAs

•

M1 ProASIC3 Devices—ARM Cortex -M1 Soft Processor

Available with or without Debug

ProASIC3 Devices

Cortex-M1 Devices

System Gates

A3P015

A3P030

A3P060 A3P125

A3P250

A3P400

A3P600

A3P1000

M1A3P250 M1A3P400

M1A3P600 M1A3P1000

15,000

30,000

60,000 125,000

250,000

400,000

600,000

1,000,000

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

128

384

–

256

768

–

512

1,536

1,024

3,072

2,048

6,144

–

9,216

–

13,824

108

–

24,576

144

–

FlashROM Kbits

Secure (AES) ISP

–

Yes

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

157

194

235

300

Notes:

1. A3P015 is not recommended for new designs.

2. Refer to the Cortex-M1 product brief for more information.

3. AES is not available for Cortex-M1 ProASIC3 devices.

4. Six chip (main) and three quadrant global networks are available for A3P060 and above.

5. The M1A3P250 device does not support this package.

6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.

7. Package not available.

† A3P015 and A3P030 devices do not support this feature.

‡ Supported only by A3P015 and A3P030 devices.

March 2016

12 3 4 5 6 7...221

中文翻译

下载PDF

与M1A3P400-1PQ208Y相关器件

型号	品牌	获取价格	描述	数据表
M1A3P400-1PQ208YI	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PQFP208, 28 X 28 MM, 3.40 MM
M1A3P400-1PQG144	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
M1A3P400-1PQG144ES	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
M1A3P400-1PQG144I	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
M1A3P400-1PQG144PP	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
M1A3P400-1PQG208	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, 350MHz, CMOS, PQFP208, 28 X 28 MM,
M1A3P400-1PQG208I	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PQFP208, 28 X 28 MM, 3.40 MM
M1A3P400-1PQG208IY	MICROSEMI	获取价格	Field Programmable Gate Array,
M1A3P400-1PQG208Y	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PQFP208
M1A3P400-1VQ144	ACTEL	获取价格	ProASIC3 Flash Family FPGAs

与M1A3P400-1PQ208Y相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

8
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

9
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

32

产品中心

服务支持

精选活动

关于我们

帮助中心

M1A3P400-1PQ208Y

M1A3P400-1PQ208Y 技术参数

M1A3P400-1PQ208Y 数据手册

与M1A3P400-1PQ208Y相关器件

与M1A3P400-1PQ208Y相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

M1A3P400-1PQ208Y

M1A3P400-1PQ208Y 技术参数

M1A3P400-1PQ208Y 数据手册

与M1A3P400-1PQ208Y相关器件

与M1A3P400-1PQ208Y相关文章

您还可以找

您在本页遇到什么问题？