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M1025-11-172.6423LF PDF预览

M1025-11-172.6423LF

更新时间: 2024-02-29 12:33:14
品牌 Logo 应用领域
艾迪悌 - IDT ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
14页 467K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

M1025-11-172.6423LF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Transferred零件包装代码:LCC
包装说明:QCCN,针数:36
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44Is Samacsys:N
JESD-30 代码:S-CQCC-N36JESD-609代码:e3
长度:8.99 mm功能数量:1
端子数量:36最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:3.1 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.635 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.99 mm
Base Number Matches:1

M1025-11-172.6423LF 数据手册

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P r o d u c t D a t a S h e e t  
Integrated  
Circuit  
Systems, Inc.  
M1025/26  
VCSO BASED CLOCK PLL WITH AUTOSWITCH  
GENERAL DESCRIPTION  
The M1025/26 is a VCSO (Voltage Controlled SAW  
Oscillator) based clock jitter  
PIN ASSIGNMENT (9 x 9 mm SMT)  
attenuator PLL designed for clock  
jitter attenuation and frequency  
translation. The device is ideal for  
generating the transmit reference  
clock for optical network systems  
supporting up to 2.5Gb data rates.  
It can serve to jitter attenuate a  
MR_SEL2  
MR_SEL0  
MR_SEL1  
LOL  
P_SEL0  
P_SEL1  
nFOUT  
FOUT  
28  
29  
30  
31  
18  
17  
16  
15  
14  
13  
12  
11  
10  
M1025  
M1026  
stratum reference clock or a recovered clock in loop  
timing mode. The M1025/26 module includes a  
proprietary SAW (surface acoustic wave) delay line as  
part of the VCSO. This results in a high frequency,  
high-Q, low phase noise oscillator that assures low  
intrinsic output jitter.  
NBW  
VCC  
32  
33  
34  
35  
36  
GND  
REF_ACK  
AUTO  
VCC  
( T o p V i e w )  
DNC  
DNC  
DNC  
GND  
FEATURES  
Integrated SAW delay line; low phase jitter of < 0.5ps  
rms, typical (12kHz to 20MHz)  
Figure 1: Pin Assignment  
Output frequencies of 62.5 to 175 MHz  
(Specify VCSO output frequency at time of order)  
Example I/O Clock Frequency Combinations  
Using M1025-11-155.5200 or M1026-11-155.5200  
LVPECL clock output (CML and LVDS options available)  
Reference clock inputs support differential LVDS,  
LVPECL, as well as single-ended LVCMOS, LVTTL  
PLL Ratio  
(Pin Selectable)  
Output Clock  
Input Reference  
Clock (MHz)  
Loss of Lock (LOL) output pin; Narrow Bandwidth  
control input (NBW pin)  
(MHz)  
(Pin Selectable)  
(M1025)  
(M1026)  
19.44 or 38.88  
(M1025) (M1026)  
AutoSwitch (AUTO pin) - automatic (non-revertive)  
reference clock reselection upon clock failure  
8 or 4  
155.52  
or  
77.76  
77.76  
155.52  
622.08  
2
1
0.25  
Acknowledge pin (REF_ACK pin) indicates the actively  
selected reference input  
Hitless Switching (HS) options with or without Phase  
Build-out (PBO) to enable SONET (GR-253) /SDH  
(G.813) MTIE and TDEV compliance during reselection  
Table 1: Example I/O Clock Frequency Combinations  
Pin-selectable feedback and reference divider ratios  
Single 3.3V power supply  
Small 9 x 9 mm SMT (surface mount) package  
SIMPLIFIED BLOCK DIAGRAM  
Loop Filter  
M1025/26  
NBW  
PLL  
Phase  
MUX  
Detector  
DIF_REF0  
nDIF_REF0  
0
R Div  
VCSO  
DIF_REF1  
nDIF_REF1  
1
REF_ACK  
REF_SEL  
M Divider  
0
LOL  
Phase  
1
AUTO  
Detector  
LOL  
Auto  
Ref Sel  
FOUT  
4
2
M/R Divider  
LUT  
P Divider  
nFOUT  
MR_SEL3:0  
P_SEL1:0  
TriState  
(1, 2, or TriState)  
P Divider  
LUT  
Figure 2: Simplified Block Diagram  
M1025/26 Datasheet Rev 1.0  
Revised 28Jul2004  
M1025/26 VCSO Based Clock PLL with AutoSwitch  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  

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