Datasheet > M1025-1Z-156.2500

M1025-1Z-156.2500

更新时间： 2024-02-24 06:34:50

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
14页	341K
描述
VCSO BASED CLOCK PLL WITH AUTOSWITCH

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P r o d u c t D a t a S h e e t

Integrated

Circuit

Systems, Inc.

M1025/26

VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERAL DESCRIPTION

The M1025/26 is a VCSO (Voltage Controlled SAW

Oscillator) based clock jitter

PIN ASSIGNMENT (9 x 9 mm SMT)

attenuator PLL designed for clock

jitter attenuation and frequency

translation. The device is ideal for

generating the transmit reference

clock for optical network systems

supporting up to 2.5Gb data rates.

It can serve to jitter attenuate a

MR_SEL2

MR_SEL0

MR_SEL1

LOL

P_SEL0

P_SEL1

nFOUT

FOUT

M1025

M1026

stratum reference clock or a recovered clock in loop

timing mode. The M1025/26 module includes a

proprietary SAW (surface acoustic wave) delay line as

part of the VCSO. This results in a high frequency,

high-Q, low phase noise oscillator that assures low

intrinsic output jitter.

NBW

VCC

GND

REF_ACK

AUTO

VCC

( T o p V i e w )

DNC

GND

FEATURES

◆ Integrated SAW delay line; low phase jitter of < 0.5ps

rms, typical (12kHz to 20MHz)

Figure 1: Pin Assignment

◆ Output frequencies of 62.5 to 175 MHz

(Specify VCSO output frequency at time of order)

Example I/O Clock Frequency Combinations

Using M1025-11-155.5200 or M1026-11-155.5200

◆ LVPECL clock output (CML and LVDS options available)

◆ Reference clock inputs support differential LVDS,

LVPECL, as well as single-ended LVCMOS, LVTTL

PLL Ratio

(Pin Selectable)

Output Clock

Input Reference

Clock (MHz)

◆ Loss of Lock (LOL) output pin; Narrow Bandwidth

control input (NBW pin)

(MHz)

(Pin Selectable)

(M1025)

(M1026)

19.44 or 38.88

(M1025) (M1026)

◆ AutoSwitch (AUTO pin) - automatic (non-revertive)

reference clock reselection upon clock failure

8 or 4

155.52

77.76

155.52

622.08

0.25

◆ Acknowledge pin (REF_ACK pin) indicates the actively

selected reference input

◆ Hitless Switching (HS) options with or without Phase

Build-out (PBO) to enable SONET (GR-253) /SDH

(G.813) MTIE and TDEV compliance during reselection

Table 1: Example I/O Clock Frequency Combinations

◆ Pin-selectable feedback and reference divider ratios

◆ Single 3.3V power supply

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop Filter

M1025/26

NBW

PLL

Phase

MUX

Detector

DIF_REF0

nDIF_REF0

R Div

VCSO

DIF_REF1

nDIF_REF1

REF_ACK

REF_SEL

M Divider

LOL

Phase

AUTO

Detector

LOL

Auto

Ref Sel

FOUT

M/R Divider

LUT

P Divider

nFOUT

MR_SEL3:0

P_SEL1:0

TriState

(1, 2, or TriState)

P Divider

LUT

Figure 2: Simplified Block Diagram

M1025/26 Datasheet Rev 1.0

Revised 28Jul2004

M1025/26 VCSO Based Clock PLL with AutoSwitch

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...14

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