Datasheet > LY6225616MN-55SL

LY6225616MN-55SL

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
台湾来扬 - LYONTEK		静态存储器
页数	文件大小	规格书
14页	194K
描述
SRAM,

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LY6225616MN-55SL 数据手册

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LY6225616

256K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.1

WRITE CYCLE 3 (LB#,UB# Controlled)

(1,2,5,6)

tWC

Address

tAW

tWR

CE#

tAS

t^CW

tBW

LB#,UB#

WE#

tWP

tWHZ

High-Z

Dout

Din

(4)

tDW

tDH

Data Valid

Notes :

1.WE#,CE#, LB#, UB# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

3.During a WE# controlled write cycle with OE# low, t_WPmust be greater than t_WHZ+ t_DWto allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance

state.

6.t_OWand t_WHZare specified with C_L= 5pF. Transition is measured ±500mV from steady state.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

1...6 7 8910 11 12...14

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