Datasheet > LY6225616MN-55SL

LY6225616MN-55SL

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
台湾来扬 - LYONTEK		静态存储器
页数	文件大小	规格书
14页	194K
描述
SRAM,

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数据手册

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LY6225616MN-55SL 数据手册

LY6225616

256K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.1

AC TEST CONDITIONS

Input Pulse Levels

0.2V to V_CC- 0.2V

Input Rise and Fall Times

Input and Output Timing Reference Levels

Output Load

3ns

1.5V

C_L= 30pF + 1TTL, I_OH/I_OL= -2mA/4mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER

SYM. LY6225616-35 LY6225616-45 LY6225616-55 LY6225616-70 UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Enable Access Time

Chip Enable to Output in Low-Z

Output Enable to Output in Low-Z t_OLZ

Chip Disable to Output in High-Z t_CHZ

Output Disable to Output in High-Z t_OHZ

Output Hold from Address Change t_OH

t_RC

t_AA

t_ACE

t_OE

t_CLZ

LB#, UB# Access Time

LB#, UB# to High-Z Output

LB#, UB# to Low-Z Output

t_BA

t_BHZ

t_BLZ

(2) WRITE CYCLE

PARAMETER

SYM. LY6225616-35 LY6225616-45 LY6225616-55 LY6225616-70 UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

t_WC

t_AW

t_CW

t_AS

t_WP

t_WR

t_DW

Address Valid to End of Write

Chip Enable to End of Write

Address Set-up Time

Write Pulse Width

Write Recovery Time

Data to Write Time Overlap

Data Hold from End of Write Time t_DH

Output Active from End of Write

Write to Output in High-Z

t_OW

t_WHZ

t_BW

LB#, UB# Valid to End of Write

*These parameters are guaranteed by device characterization, but not production tested.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

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