Datasheet
JUNE 1999
Revision2.0
LXT6051
STM-1/0 SDH Overhead Terminator
General Description
Features
The LXT6051 Overhead Terminator implements the
Regenerator Section Termination, Multiplexer Section
Termination and Higher Order Path Termination in STM-0
(51Mb/s) and STM-1 (155Mb/s) multiplexers. It provides
micro-controller access for performance monitoring, alarm
detection and configuration for transmit and receive paths.
When used with the LXT6251 (21E1 Mapper), a complete
solution for a 21 E1 or a 63 E1 Multiplexer is created.
• Performs Regenerator Section, Multiplexer Section,
and Higher Order Path Overhead Processing for
STM-1 and STM-0 signals.
• Byte parallel interface for STM-1 or STM-0, with
byte alignment performed internally. Serial NRZ or
B3ZS interface option for STM-0.
• Demultiplexes STM-0/STM-1 signals to Telecom Bus
output with optional pointer processor re-timing.
• Multiplexes Telecom Bus data into STM-0 or STM-1
signals with pointer processing.
The LXT6051 is compliant with the latest releases of ITU-
T G.703 and G.707. It provides all the alarm and control
features to easily implement the multiplexer described in
ITU-T G.783.
• Compatible with 1+1 protected ITU architecture.
• Records all RSOH, MSOH, and HPOH alarms. One
second counters for B1, B2, B3, M1 REI and G1 REI.
• Full J0/J1 trace identifier processing.
Applications
• Serial access to STM-1 user-defined, media-
dependent and national bytes.
• Dedicated pins for serial access or pass-through
feature for E1, E2, F1, F2, F3, D1-D3 & D4-D12
bytes.
• SDH Terminal Mux/ADM for microwave radio
• ADM fiber ring Mux
• Digital Loop Carrier (NGDLC) Systems
• Digital Cross-Connect System
• Low power CMOS technology with 3.3V core and 5V
I/O in PQFP-208 package.
• IEEE 1149.1 Boundary Scan (JTAG) support.
LXT6051
Block Diagram
SETS
POH
Serial Accesses
MMSP
Bus
SOH
Serial Accesses
LXT6051
OHT
Transm it
Master
Clock In
TX
4
TBus Tim ing
AU-3/4 &
VC-3/4
Transmit Processor
STM -0 / STM -1
Transmit Section
Term ination &
Protection Function
(RST, M ST, M SP)
Transmit
Tx Clock out
Telecom
Bus Add
Interface
6.48M/19.44M Clock
Data
Telecom Bus Data
(HPT, M SA (PP))
1
8
or 8 (STM-0)
(STM -1)
LXT6251
21 Channel
M apper
STM-0/1
Line
Interface
Microcontroller Interface (Intel/Motorola selectable)
1
8
or
8 (STM-0)
AU-3/4 &
VC-3/4
Receive Processor
(STM -1)
Data
Clock
LOS
Receive
Telecom
Bus
Drop
Interface
STM -0 / STM -1
Receive Section
Term ination &
Telecom Bus Data
6.48M/19.44M Clock
Protection Function
(RST, M ST, M SP)
(M SA, HPT &
Retiming)
TBus Tim ing
4
RX
Optional retim ing
Clock & tim ing
POH
Serial Accesses
DMSP
Bus
SOH
Serial Accesses
LXT6051_DS_REV2.FM - 7/6/99
Refer to www.level1.com for most current information.
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