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LX256V-35F484C

更新时间： 2024-11-26 19:47:15
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
66页 350K
描述
Crossbar Switch, CMOS, PBGA484, FPBGA-484

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LX256V-35F484C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：FPBGA-484针数：484
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.68
Base Number Matches：1

LX256V-35F484C 数据手册

 浏览型号LX256V-35F484C的Datasheet PDF文件第2页浏览型号LX256V-35F484C的Datasheet PDF文件第3页浏览型号LX256V-35F484C的Datasheet PDF文件第4页浏览型号LX256V-35F484C的Datasheet PDF文件第5页浏览型号LX256V-35F484C的Datasheet PDF文件第6页浏览型号LX256V-35F484C的Datasheet PDF文件第7页 
ispGDX2V/B/C Family  
High Performance Interfacing and Switching  
Preliminary Data Sheet  
March 2004  
• Programmable drive strength  
• sysHSI Blocks provide up to 16 high-speed  
channels  
Features  
■ High Performance Bus Switching  
• High bandwidth  
– Serializer/de-serializer (SERDES) included  
– Clock Data Recovery (CDR) built in  
– 800 Mbps per channel  
– LVDS differential support  
– 10B/12B support  
– Up to 12.8 Gbps (SERDES)  
– Up to 38 Gbps (without SERDES)  
• Up to 16 (15x10) FIFOs for data buffering  
• High speed performance  
– f  
= 360MHz  
MAX  
- Encoding / decoding  
- Bit alignment  
- Symbol alignment  
– t = 3.0ns  
PD  
– t = 2.9ns  
CO  
– t = 2.0ns  
S
– 8B/10B support  
• Built-in programmable control logic capability  
• I/O intensive: 64 to 256 I/Os  
• Expanded MUX capability up to 188:1 MUX  
- Bit alignment  
- Symbol alignment  
– Source Synchronous support  
■ sysCLOCK™ PLL  
■ Flexible Programming and Testing  
• IEEE 1532 compliant In-System Programmabil-  
ity (ISP™)  
• Frequency synthesis and skew management  
• Clock multiply and divide capability  
• Clock shifting up to +/-2.35ns in 335ps steps  
• Up to four PLLs  
• Boundary scan test through IEEE 1149.1  
interface  
• 3.3V, 2.5V or 1.8V power supplies  
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL  
interfaces  
■ sysIO™ Interfacing  
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for  
standard board interfaces  
• SSTL 2/3 Class I and II support  
• HSTL Class I, III and IV support  
• GTL+, PCI-X for bus interfaces  
• LVPECL, LVDS and Bus LVDS differential support  
• Hot socketing  
Introduction  
The ispGDX2™ family is Lattice’s second generation in-  
system programmable generic digital crosspoint switch  
for high speed bus switching and interface applications.  
Table 1. ispGDX2 Family Selection Guide  
ispGDX2-64  
ispGDX2-128  
ispGDX2-256  
256  
I/Os  
64  
128  
GDX Blocks  
4
3.0ns  
8
3.2ns  
16  
t
t
t
f
3.5ns  
PD  
S
2.0ns  
2.0ns  
2.0ns  
2.9ns  
3.1ns  
3.2ns  
CO  
MAX  
(Toggle)  
360MHz  
3.2Gbps  
11Gbps  
4
330MHz  
6.4Gbps  
21Gbps  
8
300MHz  
12.8Gbps  
38Gbps  
16  
SERDES2  
Without SERDES1  
Max Bandwidth  
800Mbps Duplex Channels  
LVDS/Bus LVDS (Pairs)  
PLLs  
32  
64  
128  
2
2
4
Package  
100-ball fpBGA  
208-ball fpBGA  
484-ball fpBGA  
1. f  
(Toggle) * maximum I/Os divided by 2.  
MAX  
2. Max number of SERDES channels per device * 800Mbps  
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
1
gdx2fam_07  
 
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LX256V-35F484C 替代型号

型号 品牌 替代类型 描述 数据表
LX256V-35FN484C LATTICE

类似代替

 Crossbar Switch, CMOS, PBGA484, LEAD FREE, FPBGA-484

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