Datasheet > LX256VCF1003

LX256VCF1003

更新时间： 2024-11-26 04:19:23

品牌	Logo	应用领域
莱迪思 - LATTICE		开关
页数	文件大小	规格书
72页	531K
描述
High Performance Interfacing and Switching

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

LX256VCF1003 数据手册

™

ispGDX2 Family

High Performance Interfacing and Switching

September 2005

Data Sheet

■ Two Options Available

Features

• High-performance sysHSI (standard part number)

• Low-cost, no sysHSI (“E-Series”)

■ High Performance Bus Switching

• High bandwidth

■ sysHSI Blocks Provide up to 16 High-speed

Channels

– Up to 12.8 Gbps (SERDES)

– Up to 38 Gbps (without SERDES)

• Up to 16 (15x10) FIFOs for data buffering

• High speed performance

• Serializer/de-serializer (SERDES) included

• Clock Data Recovery (CDR) built in

• 800 Mbps per channel

• LVDS differential support

• 10B/12B support

– f

= 360MHz

MAX

– t = 3.0ns

– t = 2.9ns

– Encoding / decoding

– Bit alignment

– Symbol alignment

– t = 2.0ns

• Built-in programmable control logic capability

• I/O intensive: 64 to 256 I/Os

• Expanded MUX capability up to 188:1 MUX

• 8B/10B support

– Bit alignment

– Symbol alignment

• Source Synchronous support

■ sysCLOCK™ PLL

• Frequency synthesis and skew management

• Clock multiply and divide capability

• Clock shifting up to +/-2.35ns in 335ps steps

• Up to four PLLs

■ Flexible Programming and Testing

• IEEE 1532 compliant In-System Programmabil-

ity (ISP™)

■ sysIO™ Interfacing

• Boundary scan test through IEEE 1149.1

interface

• 3.3V, 2.5V or 1.8V power supplies

• 5V tolerant I/O for LVCMOS 3.3 and LVTTL

interfaces

• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for

standard board interfaces

• SSTL 2/3 Class I and II support

• HSTL Class I, III and IV support

• GTL+, PCI-X for bus interfaces

• LVPECL, LVDS and Bus LVDS differential support

• Hot socketing

• Programmable drive strength

Table 1. ispGDX2 Family Selection Guide

ispGDX2-64/E

ispGDX2-128/E

ispGDX2-256/E

I/Os

128

256

GDX Blocks

3.0ns

3.2ns

3.5ns

2.0ns

2.9ns

3.1ns

3.2ns

MAX

(Toggle)

360MHz

3.2Gbps

11Gbps

330MHz

6.4Gbps

21Gbps

300MHz

12.8Gbps

38Gbps

SERDES^{1, 2}

Without SERDES³

Max Bandwidth

sysHSI Channels²

LVDS/Bus LVDS (Pairs)

PLLs

128

Package

100-ball fpBGA

208-ball fpBGA

484-ball fpBGA

1. Max number of SERDES channels per device * 800Mbps

2. “E-Series” does not support sysHSI.

3. f

(Toggle) * maximum I/Os divided by 2.

MAX

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

gdx2fam_13

12 3 4 5 6 7...72

中文翻译

下载PDF

与LX256VCF1003相关器件

型号	品牌	获取价格	描述	数据表
LX256VCF10032	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF10035	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF1005	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF2083	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF20832	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF20835	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF2085	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF4843	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF48432	LATTICE	获取价格	High Performance Interfacing and Switching
LX256VCF48435	LATTICE	获取价格	High Performance Interfacing and Switching

与LX256VCF1003相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

44
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

33
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

61
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

58

产品中心

服务支持

精选活动

关于我们

帮助中心

LX256VCF1003

LX256VCF1003 数据手册

与LX256VCF1003相关器件

与LX256VCF1003相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

LX256VCF1003

LX256VCF1003 数据手册

与LX256VCF1003相关器件

与LX256VCF1003相关文章

您还可以找

您在本页遇到什么问题？