ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢂ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢆꢇ ꢂꢈ
ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢌꢀ ꢑꢌꢒ ꢒ ꢐꢎ ꢓ ꢈꢔꢐ ꢀ
ꢕ ꢖꢔ ꢗ ꢘ ꢙꢀꢔꢈꢔ ꢐ ꢚ ꢌꢔ ꢏꢌ ꢔꢀ
SCES124L − DECEMBER 1997 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V
Operation
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 6 ns at 5 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
− 1000-V Charged-Device Model (C101)
SN54LV125A . . . J OR W PACKAGE
SN74LV125A . . . D, DB, DGV, N, NS,
OR PW PACKAGE
SN74LV125A . . . RGY PACKAGE
(TOP VIEW)
SN54LV125A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
14
3
2
1
20 19
18
1OE
1A
V
CC
13 4OE
1
2
3
4
5
6
7
14
4A
NC
4Y
1Y
NC
4
5
6
7
8
1A
1Y
13 4OE
12 4A
2
3
4
5
6
17
16
12
11
10
9
1Y
4A
2OE
NC
11
10
9
2OE
2A
4Y
2OE
2A
4Y
15 NC
14
9 10 11 12 13
3OE
3A
3OE
3A
3OE
2A
2Y
2Y
7
8
8
GND
3Y
NC − No internal connection
description/ordering information
The ‘LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V V
operation.
CC
These devices feature independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
SN74LV125AN
SN74LV125AN
LV125A
QFN − RGY
Reel of 1000
Tube of 50
SN74LV125ARGYR
SN74LV125AD
SOIC − D
LV125A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV125ADR
SN74LV125ANSR
SN74LV125ADBR
SN74LV125APW
SN74LV125APWR
SN74LV125APWT
SN74LV125ADGVR
SNJ54LV125AJ
SOP − NS
74LV125A
LV125A
−40°C to 85°C
SSOP − DB
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV125A
TVSOP − DGV
CDIP − J
LV125A
SNJ54LV125AJ
SNJ54LV125AW
SNJ54LV125AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV125AW
SNJ54LV125AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢌ ꢁ ꢄꢐꢀꢀ ꢚ ꢔꢗ ꢐꢎꢕ ꢖꢀ ꢐ ꢁ ꢚꢔꢐꢍ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢏꢎ ꢚ ꢍ ꢌ ꢧꢔ ꢖꢚ ꢁ
ꢛ
ꢍ
ꢈ
ꢔ
ꢈ
ꢝ
ꢥ
ꢨ
ꢠ
ꢩ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢢ
ꢩ
ꢩ
ꢤ
ꢥ
ꢛ
ꢦ
ꢞ
ꢠ
ꢨ
ꢪ
ꢢ
ꢫ
ꢬ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢟ
ꢦ
ꢤ
ꢭ
ꢏ
ꢩ
ꢠ
ꢟ
ꢢ
ꢡ
ꢛ
ꢞ
ꢡ
ꢠ
ꢥ
ꢨ
ꢠ
ꢩ
ꢣ
ꢛ
ꢠ
ꢞ
ꢪ
ꢤ
ꢡ
ꢝ
ꢨ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢪ
ꢤ
ꢩ
ꢛ
ꢜ
ꢤ
ꢛ
ꢤ
ꢩ
ꢣ
ꢞ
ꢠ
ꢨ
ꢔ
ꢤ
ꢮ
ꢦ
ꢞ
ꢖ
ꢥ
ꢞ
ꢛ
ꢩ
ꢢ
ꢣ
ꢤ
ꢥ
ꢛ
ꢞ
ꢞ
ꢛ
ꢦ
ꢥ
ꢟ
ꢦ
ꢩ
ꢟ
ꢯ
ꢦ
ꢩ
ꢩ
ꢦ
ꢥ
ꢛ
ꢰ
ꢭ
ꢏ
ꢩ
ꢠ
ꢟ
ꢢ
ꢡ
ꢛ
ꢝ
ꢠ
ꢥ
ꢪꢦ ꢩ ꢦ ꢣ ꢤ ꢛ ꢤ ꢩ ꢞ ꢭ
ꢪ
ꢩ
ꢠ
ꢡ
ꢤ
ꢞ
ꢞ
ꢝ
ꢥ
ꢱ
ꢟ
ꢠ
ꢤ
ꢞ
ꢥ
ꢠ
ꢛ
ꢥ
ꢤ
ꢡ
ꢤ
ꢞ
ꢞ
ꢦ
ꢩ
ꢝ
ꢬ
ꢰ
ꢝ
ꢥ
ꢡ
ꢬ
ꢢ
ꢟ
ꢤ
ꢛ
ꢤ
ꢞ
ꢛ
ꢝ
ꢥ
ꢱ
ꢠ
ꢨ
ꢦ
ꢬ
ꢬ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265