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LTM9004 PDF预览

LTM9004

更新时间: 2024-11-13 12:09:59
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
36页 584K
描述
16-Bit, 20Msps Low Noise Dual ADC

LTM9004 数据手册

 浏览型号LTM9004的Datasheet PDF文件第2页浏览型号LTM9004的Datasheet PDF文件第3页浏览型号LTM9004的Datasheet PDF文件第4页浏览型号LTM9004的Datasheet PDF文件第5页浏览型号LTM9004的Datasheet PDF文件第6页浏览型号LTM9004的Datasheet PDF文件第7页 
LTC2270  
16-Bit, 20Msps  
Low Noise Dual ADC  
FEATURES  
DESCRIPTION  
Two-Channel Simultaneously Sampling ADC  
The LTC®2270 is a two-channel simultaneous sampling  
16-bitA/Dconverterdesignedfordigitizinghighfrequency,  
wide dynamic range signals. It is perfect for demanding  
applications with AC performance that includes 84.1dB  
SNR and 99dB spurious free dynamic range (SFDR).  
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84.1dB SNR (46μV  
99dB SFDR  
2.ꢀLSB INL(Max)  
Input Referred Noise)  
RMS  
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Low Power: 160mW Total, 80mW per Channel  
Single 1.8V Supply  
DC specs include 1LSB INL (typ), 0.2LSB DNL (typ)  
and no missing codes over temperature. The transition  
CMOS, DDR CMOS, or DDR LVDS Outputs  
Selectable Input Ranges: 1V to 2.1V  
P-P  
P-P  
noise is 1.44LSB  
.
RMS  
200MHz Full Power Bandwidth S/H  
The digital outputs can be either full rate CMOS, Double  
Data Rate CMOS, or Double Data Rate LVDS. A separate  
output power supply allows the CMOS output swing to  
range from 1.2V to 1.8V.  
Shutdown and Nap Modes  
Serial SPI Port for Configuration  
Pin Compatible with  
LTC2180: 16-Bit, 25Msps, 78mW  
+
LTC2140-14: 14-Bit, 25Msps, 50mW  
The ENC and ENC inputs may be driven differentially  
or single-ended with a sine wave, PECL, LVDS, TTL, or  
CMOS inputs. An optional clock duty cycle stabilizer al-  
lows high performance at full speed for a wide range of  
clock duty cycles.  
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64-Lead (9mm × 9mm) QFN Package  
APPLICATIONS  
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Low Power Instrumentation  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
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Software Defined Radios  
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Portable Medical Imaging  
Multi-Channel Data Acquisition  
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TYPICAL APPLICATION  
Integral Non-Linearity (INL)  
1.8V  
1.8V  
OV  
V
DD  
DD  
2.0  
1.5  
CH 1  
ANALOG  
INPUT  
16-BIT  
D1_15  
1.0  
0.5  
S/H  
S/H  
t
t
t
ADC CORE  
CMOS,  
D1_0  
DDR CMOS  
OR DDR LVDS  
OUTPUTS  
0.0  
D2_15  
t
t
t
OUTPUT  
DRIVERS  
–0.5  
–1.0  
–1.5  
–2.0  
CH 2  
ANALOG  
INPUT  
16-BIT  
ADC CORE  
D2_0  
0
32768  
OUTPUT CODE  
49152  
65536  
16384  
20MHz  
CLOCK  
CLOCK  
CONTROL  
2270 TA02  
2270 TA01  
GND  
OGND  
2270f  
1

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