Electrical Specifications Subject to Change
LTC3589
8-Output Regulator with
2
Sequencing and I C
FEATURES
DESCRIPTION
2
The LTC®3589 is a complete power management solu-
tion for ARM and ARM-based processors and advanced
portable microprocessor systems. The device contains
three synchronous step-down DC/DC converters for
core, memory and SoC rails, a synchronous buck-boost
regulator for I/O at 3.3V to 5V, and three 250mA LDO
n
Triple I C Adjustable High Efficiency Step-Down
Switching Regulators: 1.6A, 1A, 1A
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High Efficiency 1.2A Buck-Boost Switching Regulator
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Triple 250mA LDO Regulators
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Always Alive 25mA LDO Regulator
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Flexible Pin-Strap Sequencing Operation
2
2
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I C and Independent Enable Control Pins
regulatorsforlownoiseanalogsupplies. AnI Cserialport
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Power Good and Reset Outputs
is used to control regulator enables, output voltage levels,
dynamic voltage scaling and slew rate, operating modes
and status reporting. Regulator start-up is sequenced by
connecting regulator outputs to enable pins in the desired
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Dynamic Voltage Scaling and Slew Rate Control
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Selectable 2.25MHz or 1.12MHz Switching Frequency
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Pushbutton ON/OFF Control with System Reset
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2
10μA Standby Current
order or via the I C port. System power-on, power-off
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40-Pin 6mm × 6mm × 0.75mm QFN
and reset functions are controlled by pushbutton inter-
2
face, pin inputs, or I C interface. The LTC3589 supports
APPLICATIONS
i.MX, PXA and OMAP processors with eight independent
rails at appropriate power levels, dynamic control and
sequencing. Other features include interface signals such
as the VSTB pin that toggles between programmed run
and standby output voltages on up to four rails simultane-
ously. The device is available in a low profile 40-pin 6mm
× 6mm exposed pad QFN package.
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Handheld Instruments and Scanners
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Portable Industrial Devices
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Automotive Infotainment
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Portable Medical Devices
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High End Consumer Devices
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Multirail Systems
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Supports Freescale i.MX, Marvell PXA and Other
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered
trademarks, Hot Swap and Bat-track are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Application Processors
TYPICAL APPLICATION
V
2.7V TO 5.5V
IN
Start-Up Sequence
V
V
IN
CORE
VRTC 1.2V
AT 25mA
SW1
SW2
SW3
0.6V TO 1.2V
AT 1.6A
LDO1_STDBY
I/O
V
MEMORY
0.9V TO 1.2V
AT 250mA
SRAM
LTC3589
WAKE
(1V/DIV)
0.9V TO 1.8V
AT 1A
LDO2
V
SRAM
V
SOC
ANALOG 1.8V
AT 250mA
ANALOG
LDO3
LDO4
0.625V TO 1.25V
AT 1A
DDR
MEMORY
V
SOC
1.8V, 2.5V,
2.8V, 3.3V
AT 250mA
MEMORY
3
7
SW4AB
SW4CD
BB_OUT
2
V
CORE
I C
I/O
ENABLES
VSTB
3589 TA01b
500μs/DIV
3.3V AT 1.2A
FROM μPROCESSOR
OR 5V AT 1A
PWR_ON
WAKE
HDD
OR I/O
ON (PB)
PBSTAT
PGOOD
RSTO
GND
3589 TA01a
3589p
1