LTC2325-16
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
(Note 11)
(Note 11)
(Note 11)
MIN
TYP
MAX
UNITS
ns
l
l
l
t
t
t
Bus Relinquish Time After CNV↑
SDO Valid Delay from CNV↓
SCK Delay Time to CNV↑
3
3
DCNVSDOZ
DCNVSDOV
DSCKHCNVH
ns
0
ns
CMOS I/O Mode, DDR, CMOS/LVDS = GND, SDR/ DDR = OV
DD
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
SCK Period
18.2
8.2
8.2
0
ns
ns
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCK Low Time
SCKH
SCKL
SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)
1.5
4.5
3
HSDO_DDR
DSCKCLKOUT
DCNVSDOZ
DCNVSDOV
DSCKHCNVH
L
SCK to CLKOUT Delay
(Note 12)
(Note 11)
(Note 11)
(Note 11)
2
Bus Relinquish Time After CNV↑
SDO Valid Delay from CNV↓
SCK Delay Time to CNV↑
3
0
LVDS I/O Mode, SDR, CMOS/LVDS = OV , SDR/DDR = GND
DD
l
l
l
l
l
l
t
t
t
t
t
t
SCK Period
9.1
4.1
4.1
0
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCK Low Time
SCKH
SCKL
SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF OV = 2.5V
1.5
4
HSDO_SDR
DSCKCLKOUT
DSCKHCNVH
L
DD
SCK to CLKOUT Delay
OV = 2.5V
2
DD
SCK Delay Time to CNV↑
(Note 11)
0
LVDS I/O Mode, DDR, CMOS/LVDS = OV , SDR/DDR = OV
DD
DD
l
l
l
l
l
l
t
t
t
t
t
t
SCK Period
18.2
8.2
8.2
0
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCK Low Time
SCKH
SCKL
SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF OV = 2.5V
1.5
4
HSDO_DDR
DSCKCLKOUT
DSCKHCNVH
L
DD
SCK to CLKOUT Delay
OV = 2.5V
2
DD
SCK Delay Time to CNV↑
(Note 11)
0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 4.096V input
with REF = 4.096V.
Note 2: All voltage values are with respect to GND.
Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer
Note 3: When these pin voltages are taken below GND, or above V or
must be turned off by setting REFBUFEN = 0V.
DD
OV , they will be clamped by internal diodes. This product can handle input
DD
Note 10: f
= 5MHz, I
varies proportionally with sample rate.
SMPL
REFOUT1,2,3,4
currents up to 100mA below GND, or above V or OV , without latch-up.
DD
DD
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OV = 1.71V and OV = 2.5V.
Note 13: t
rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OV
logic levels.
Note 4: V = 5V, OV = 2.5V, REFOUT1,2,3,4 = 4.096V, f = 5MHz.
SMPL
DD
DD
DD
DD
Note 5: Recommended operating conditions.
of 9.1ns allows a shift clock frequency up to 105MHz for
SCK
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS
DD
232516fa
6
For more information www.linear.com/LTC2325-16
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