Datasheet > LTC2182

LTC2182

更新时间： 2023-12-20 18:44:30

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
36页	3937K
描述
16 位、65Msps、低功率、双通道 ADC

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数据手册

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LTC2182 数据手册

LTC2182/LTC2181/LTC2180

16-Bit, 65Msps/

40Msps/25Msps Low Power

Dual ADCs

FEATURES

DESCRIPTION

The LTC^®2182/LTC2181/LTC2180 are two-channel si-

multaneous sampling 16-bit A/D converters designed for

digitizinghighfrequency,widedynamicrangesignals.They

are perfect for demanding communications applications

with AC performance that includes 77dB SNR and 90dB

spurious free dynamic range (SFDR). Ultralow jitter of

Two-Channel Simultaneously Sampling ADC

77dB SNR

90dB SFDR

Low Power: 160mW/115mW/78mW Total

80mW/58mW/39mW per Channel

Single 1.8V Supply

CMOS, DDR CMOS, or DDR LVDS Outputs

0.07ps

allows undersampling of IF frequencies with

RMS

Selectable Input Ranges: 1V to 2V

excellent noise performance.

P-P

550MHz Full Power Bandwidth S/H

Optional Data Output Randomizer

Optional Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

Serial SPI Port for Configuration

64-Pin (9mm × 9mm) QFN Package

DC specs include 2LSB INL (typ), 0.5LSB DNL (typ)

and no missing codes over temperature. The transition

noise is 3.3LSB

RMS

The digital outputs can be either full rate CMOS, Double

Data Rate CMOS, or Double Data Rate LVDS. A separate

output power supply allows the CMOS output swing to

range from 1.2V to 1.8V.

APPLICATIONS

–

The ENC and ENC inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An optional clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

Communications

Cellular Base Stations

Software Defined Radios

Portable Medical Imaging

Multi-Channel Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Nondestructive Testing

TYPICAL APPLICATION

2-Tone FFT, f_IN= 70MHz and 69MHz

1.8V

–10

–20

CH 1

ANALOG

INPUT

16-BIT

D1_15

–30

–40

–50

–60

–70

S/H

•

ADC CORE

CMOS,

D1_0

DDR CMOS

OR DDR LVDS

OUTPUTS

D2_15

•

OUTPUT

DRIVERS

CH 2

ANALOG

INPUT

–80

–90

–100

–110

–120

16-BIT

ADC CORE

D2_0

FREQUENCY (MHz)

65MHz

CLOCK

CONTROL

218210 TA01b

218210 TA01a

GND

OGND

218210f

12 3 4 5 6 7...36

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