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LTC2182IUP#PBF PDF预览

LTC2182IUP#PBF

更新时间: 2024-02-01 13:42:03
品牌 Logo 应用领域
凌特 - Linear 转换器
页数 文件大小 规格书
36页 3937K
描述
LTC2182 - 16-Bit, 65Msps Low Power Dual ADCs; Package: QFN; Pins: 64; Temperature Range: -40°C to 85°C

LTC2182IUP#PBF 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:HVQCCN,
针数:64Reach Compliance Code:compliant
ECCN代码:3A991.C.4HTS代码:8542.39.00.01
风险等级:3.69最大模拟输入电压:1.25 V
最小模拟输入电压:0.7 V转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-PQCC-N64JESD-609代码:e3
长度:9 mm最大线性误差 (EL):0.0092%
模拟输入通道数量:2位数:16
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
采样速率:65 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:0.8 mm标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9 mmBase Number Matches:1

LTC2182IUP#PBF 数据手册

 浏览型号LTC2182IUP#PBF的Datasheet PDF文件第2页浏览型号LTC2182IUP#PBF的Datasheet PDF文件第3页浏览型号LTC2182IUP#PBF的Datasheet PDF文件第4页浏览型号LTC2182IUP#PBF的Datasheet PDF文件第5页浏览型号LTC2182IUP#PBF的Datasheet PDF文件第6页浏览型号LTC2182IUP#PBF的Datasheet PDF文件第7页 
LTC2182/LTC2181/LTC2180  
16-Bit, 65Msps/  
40Msps/25Msps Low Power  
Dual ADCs  
FEATURES  
DESCRIPTION  
The LTC®2182/LTC2181/LTC2180 are two-channel si-  
multaneous sampling 16-bit A/D converters designed for  
digitizinghighfrequency,widedynamicrangesignals.They  
are perfect for demanding communications applications  
with AC performance that includes 77dB SNR and 90dB  
spurious free dynamic range (SFDR). Ultralow jitter of  
n
Two-Channel Simultaneously Sampling ADC  
n
77dB SNR  
n
90dB SFDR  
Low Power: 160mW/115mW/78mW Total  
n
80mW/58mW/39mW per Channel  
Single 1.8V Supply  
n
n
CMOS, DDR CMOS, or DDR LVDS Outputs  
0.07ps  
allows undersampling of IF frequencies with  
RMS  
n
Selectable Input Ranges: 1V to 2V  
excellent noise performance.  
P-P  
P-P  
n
n
n
n
n
n
550MHz Full Power Bandwidth S/H  
Optional Data Output Randomizer  
Optional Clock Duty Cycle Stabilizer  
Shutdown and Nap Modes  
Serial SPI Port for Configuration  
64-Pin (9mm × 9mm) QFN Package  
DC specs include 2LSB INL (typ), 0.5LSB DNL (typ)  
and no missing codes over temperature. The transition  
noise is 3.3LSB  
.
RMS  
The digital outputs can be either full rate CMOS, Double  
Data Rate CMOS, or Double Data Rate LVDS. A separate  
output power supply allows the CMOS output swing to  
range from 1.2V to 1.8V.  
APPLICATIONS  
+
The ENC and ENC inputs may be driven differentially  
or single-ended with a sine wave, PECL, LVDS, TTL, or  
CMOS inputs. An optional clock duty cycle stabilizer al-  
lows high performance at full speed for a wide range of  
clock duty cycles.  
n
Communications  
n
Cellular Base Stations  
n
Software Defined Radios  
n
Portable Medical Imaging  
n
Multi-Channel Data Acquisition  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
n
Nondestructive Testing  
TYPICAL APPLICATION  
2-Tone FFT, fIN = 70MHz and 69MHz  
1.8V  
1.8V  
OV  
V
DD  
DD  
0
–10  
–20  
CH 1  
ANALOG  
INPUT  
16-BIT  
D1_15  
–30  
–40  
–50  
–60  
–70  
S/H  
S/H  
ADC CORE  
CMOS,  
D1_0  
DDR CMOS  
OR DDR LVDS  
OUTPUTS  
D2_15  
OUTPUT  
DRIVERS  
CH 2  
ANALOG  
INPUT  
–80  
–90  
–100  
–110  
–120  
16-BIT  
ADC CORE  
D2_0  
0
20  
10  
FREQUENCY (MHz)  
30  
65MHz  
CLOCK  
CLOCK  
CONTROL  
218210 TA01b  
218210 TA01a  
GND  
OGND  
218210f  
1

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