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LTC2183_15 PDF预览

LTC2183_15

更新时间: 2022-02-26 12:02:39
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
36页 809K
描述
16-Bit, 125/105/80Msps Low Power Dual ADCs

LTC2183_15 数据手册

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LTC2185/LTC2184/LTC2183  
16-Bit, 125/105/80Msps  
Low Power Dual ADCs  
FeaTures  
DescripTion  
The LTC®2185/LTC2184/LTC2183 are two-channel si-  
multaneous sampling 16-bit A/D converters designed for  
digitizing high frequency, wide dynamic range signals.  
They are perfect for demanding communications applica-  
tions with AC performance that includes 76.8dB SNR and  
90dB spurious free dynamic range (SFDR). Ultralow jitter  
n
Two-Channel Simultaneously Sampling ADC  
n
76.8dB SNR  
n
90dB SFDR  
n
Low Power: 370mW/308mW/200mW Total  
185mW/154mW/100mW per Channel  
n
Single 1.8V Supply  
n
of0.07ps  
allowsundersamplingofIFfrequencieswith  
CMOS, DDR CMOS, or DDR LVDS Outputs  
RMS  
n
excellent noise performance.  
Selectable Input Ranges: 1V to 2V  
P-P  
P-P  
n
n
n
n
n
n
550MHz Full Power Bandwidth S/H  
Optional Data Output Randomizer  
Optional Clock Duty Cycle Stabilizer  
Shutdown and Nap Modes  
Serial SPI Port for Configuration  
64-Pin (9mm × 9mm) QFN Package  
DC specs include 2LSB INL (typ), 0.5LSB DNL (typ)  
and no missing codes over temperature. The transition  
noise is 3.4LSB  
.
RMS  
The digital outputs can be either full rate CMOS, Double  
Data Rate CMOS, or Double Data Rate LVDS. A separate  
output power supply allows the CMOS output swing to  
range from 1.2V to 1.8V.  
applicaTions  
+
The ENC and ENC inputs may be driven differentially  
or single-ended with a sine wave, PECL, LVDS, TTL, or  
CMOS inputs. An optional clock duty cycle stabilizer al-  
lows high performance at full speed for a wide range of  
clock duty cycles.  
n
Communications  
n
Cellular Base Stations  
n
Software Defined Radios  
n
Portable Medical Imaging  
n
Multi-Channel Data Acquisition  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
n
Nondestructive Testing  
Typical applicaTion  
2-Tone FFT, fIN = 70MHz and 69MHz  
1.8V  
1.8V  
OV  
V
DD  
DD  
0
–10  
–20  
CH 1  
ANALOG  
INPUT  
16-BIT  
D1_15  
–30  
–40  
–50  
–60  
–70  
S/H  
S/H  
ADC CORE  
CMOS,  
D1_0  
DDR CMOS  
OR DDR LVDS  
OUTPUTS  
D2_15  
OUTPUT  
DRIVERS  
CH 2  
ANALOG  
INPUT  
–80  
–90  
–100  
–110  
–120  
16-BIT  
ADC CORE  
D2_0  
0
20  
30  
40  
50  
60  
10  
125MHz  
CLOCK  
CLOCK  
CONTROL  
FREQUENCY (MHz)  
218543 TA01b  
218543 TA01a  
GND  
OGND  
218543f  
1

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