LTC2142-14/
LTC2141-14/LTC2140-14
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2142-14
TYP
LTC2141-14
TYP
LTC2140-14
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
CMOS Output Modes: Full Data Rate and Double Data Rate
l
l
l
V
Analog Supply Voltage (Note 10)
Output Supply Voltage (Note 10)
Analog Supply Current DC Input
1.7
1.1
1.8
1.8
1.9
1.9
59
1.7
1.1
1.8
1.8
1.9
1.9
42
1.7
1.1
1.8
1.8
1.9
1.9
33
V
V
DD
OV
DD
I
52.7
53
37.1
37.3
27.9
28.1
mA
mA
VDD
Sine Wave Input
I
Digital Supply Current Sine Wave Input, OV = 1.2V
4.4
2.7
1.7
mA
OVDD
DD
l
P
Power Dissipation
DC Input
Sine Wave Input, OV = 1.2V
94.9
100.7
107
66.8
70.4
76
50.2
52.6
60
mW
mW
DISS
DD
LVDS Output Mode
Analog Supply Voltage (Note 10)
l
l
V
DD
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
V
V
OV
DD
Output Supply Voltage (Note 10)
I
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
54.4
55.8
38.7
40.2
29.5
30.9
mA
mA
VDD
l
l
l
63
75
46
75
37
75
I
Digital Supply Current Sine Input, 1.75mA Mode
34.3
65.7
33.9
65.3
33.7
65.1
mA
mA
OVDD
(0V = 1.8V)
Sine Input, 3.5mA Mode
DD
P
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
160
219
131
190
114
173
mW
mW
DISS
249
218
202
All Output Modes
P
P
P
Sleep Mode Power
Nap Mode Power
1
1
1
mW
mW
mW
SLEEP
NAP
10
20
10
20
10
20
Power Increase with Differential Encode Mode Enabled
(No Increase for Nap or Sleep Modes)
DIFFCLK
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2142-14
TYP
LTC2141-14
TYP
LTC2140-14
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
TYP MAX UNITS
l
f
t
Sampling Frequency
(Note 10)
1
65
1
40
1
25
MHz
S
L
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2
7.69
7.69
500 11.88 12.5
500 12.5
500
500
19
2
20
20
500
500
ns
ns
2
l
l
t
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2
7.69
7.69
500 11.88 12.5
500
500
19
2
20
20
500
500
ns
ns
H
500
2
12.5
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
AP
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.7
1.4
0.3
3.1
2.6
0.6
ns
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
SKEW
D
C
Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles
21421014fa
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