Datasheet > LTC2122

LTC2122

更新时间： 2023-12-20 18:44:53

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
50页	1428K
描述
具有JESD204B串行输出的双通道、14位、170Msps ADC

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中文翻译

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数据手册

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LTC2122 数据手册

LTC2122

Dual 14-Bit 170Msps ADC

with JESD204B Serial Outputs

FEATURES

DESCRIPTION

The LTC^®2122 is a 2-channel simultaneous sampling

170Msps 14-bit A/D converter with serial JESD204B

outputs. It is designed for digitizing high frequency,

wide dynamic range signals. It is perfect for demanding

communications applications with AC performance that

includes 70dBFS SNR and 90dBFS spurious free dynamic

range (SFDR). The 1.25GHz input bandwidth allows the

ADC to under-sample high frequencies.

6.0Gbps JESD204B Interface

Only One Output Lane Required for Both ADCs

(F ≤ 150Msps)

70dBFS SNR

90dBFS SFDR

Low Power: 751mW Total

Single 1.8V Supply

Easy to Drive 1.5V Input Range

1.25GHz Full Power Bandwidth S/H

Optional Clock Divide by Two

Optional Clock Duty Cycle Stabilizer

Low Power Sleep and Nap Modes

Serial SPI Port for Configuration

48-Lead (7mm × 7mm) QFN Package

P-P

TheJESD204BserialinterfacesimplifiesthePCBdesignby

minimizingthenumberofdatalinesrequired.At170Msps,

only two 3.4Gbps output lanes are required. For sample

rates up to 150Msps, both ADCs may share the same

output lane at up to 6.0Gbps.

–

The DEVCLK and DEVCLK inputs can be driven differen-

tially with sine wave, PECL, or LVDS signals. An optional

clock divide-by-two circuit or clock duty cycle stabilizer

maintains high performance at full speed for a wide range

of clock duty cycles.

APPLICATIONS

Communications

Cellular Base Stations

Software Defined Radios

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Medical Imaging

High Definition Video

Test and Measurement Instrumentation

TYPICAL APPLICATION

1.2V TO 1.9V

64k Point 2-Tone FFT,

f_IN= 71MHz and 69MHz,

–7dBFS, 170Msps

LTC2122

50Ω 50Ω

–20

JESD204B

LOGIC

ANALOG

INPUT

14-BIT ADC

SERIALIZER

3.4Gbps

–40

–60

CLOCK

÷ 2 OR ÷ 1

JESD204B

FPGA OR ASIC

PLL

CLOCK

1.2V TO 1.9V

–80

(170MHz OR

340MHz)

–100

–120

50Ω 50Ω

JESD204B

LOGIC

ANALOG

INPUT

14-BIT ADC

SERIALIZER

3.4Gbps

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

2122 TA01a

2122 TA01

2122fb

For more information www.linear.com/LTC2122

12 3 4 5 6 7...50

中文翻译

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与LTC2122相关器件

型号	品牌	获取价格	描述	数据表
LTC2123	Linear	获取价格	14-Bit, 250Msps to 170Msps Dual ADCs with JESD204B Outputs
LTC2123	ADI	获取价格	具有JESD204B串行输出的双通道、14位、250Msps ADC
LTC2140-12	Linear	获取价格	12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs
LTC2140-12	ADI	获取价格	12 位、25Msps、低功率、双通道 ADC
LTC2140-12_15	Linear	获取价格	12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs
LTC2140-14	Linear	获取价格	12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs
LTC2140-14	ADI	获取价格	14 位、25Msps、低功率、双通道 ADC
LTC2140-14_15	Linear	获取价格	14-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs
LTC2140CUP-14#PBF	Linear	获取价格	LTC2140-14 - 14-Bit, 25Msps Low Power Dual ADCs; Package: QFN; Pins: 64; Temperature Range
LTC2140IUP-14#PBF	Linear	获取价格	LTC2140-14 - 14-Bit, 25Msps Low Power Dual ADCs; Package: QFN; Pins: 64; Temperature Range

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