Datasheet > LTC2123

LTC2123

更新时间： 2024-09-25 01:23:03

品牌	Logo	应用领域
凌特 - Linear		/
页数	文件大小	规格书
14页	834K
描述
14-Bit, 250Msps to 170Msps Dual ADCs with JESD204B Outputs

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LTC2123 数据手册

DEMO MANUAL DC1974

LTC2123, LTC2122

14-Bit, 250Msps to 170Msps Dual

ADCs with JESD204B Outputs

DESCRIPTION

Demonstration circuit 1974 supports the LTC^®2123 14-bit

dual ADC family with JESD204B compliant CML outputs.

It was specially designed for applications that require

single-endedACcoupledinputs.TheDC1974supportsthe

LTC2123 and LTC2122 with sample rates from 250Msps

to 170Msps.

Refer to the data sheet for proper input networks for dif-

ferent input frequencies.

Design files for this circuit board are available at

http://www.linear.com/demo/DC1974

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

The specific ADC characteristics are listed in the DC1974

Variants section. The circuitry on the analog inputs is opti-

mizedforanaloginputfrequenciesfrom5MHzto400MHz.

DC1974 VARIANTS

RESOLUTION

MAXIMUM SAMPLE RATE

(Msps)

INPUT FREQUENCY

(MHz)

DC1974 VARIANTS

1974A-B

ADC PART NUMBER

LTC2123

(Bit)

250

170

5 to 400

1974A-C

LTC2122

PERFORMANCE SUMMARY ^{Specifications are at T}_A^{= 25°C}

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

ADC Supply Voltage

This Supply Must Provide Up to 700mA

Analog Input Range

1.35

1.5

250

Sampling Frequency (Device Clock Frequency)

Device Clock Level (Single-Ended at J3)

Depending on ADC (1X CLK Mode)

MHz

Minimum Logic Levels (DEV + Tied to GND)

CLK

Maximum Logic Levels (DEV + Tied to GND)

3.6

CLK

Device Clock Level (Differential Signal Across J3 and J4) Minimum Logic Levels (DEV + Not Tied to GND,

0.2

1.1

CLK

1.2V Common Mode)

Digital Inputs (ADC_SYS_REF_N, ADC_SYS_REF_P,

SYNC_N, SYNC_P)

Differential Input Voltage

1.8

1.5

Common Mode Input Range

1.2

dc1974fa

12 3 4 5 6 7...14

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