Datasheet > LTC2141-14

LTC2141-14

更新时间： 2023-12-20 18:44:07

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
38页	541K
描述
14 位、40Msps、低功率、双通道 ADC

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数据手册

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LTC2141-14 数据手册

LTC2142-14/

LTC2141-14/LTC2140-14

14-Bit, 65Msps/

40Msps/25Msps Low Power

Dual ADCs

FEATURES

DESCRIPTION

TheLTC^®2142-14/LTC2141-14/LTC2140-14are2-channel

simultaneous sampling 14-bit A/D converters designed

for digitizing high frequency, wide dynamic range signals.

They are perfect for demanding communications applica-

tions with AC performance that includes 73.2dB SNR and

90dB spurious free dynamic range (SFDR). Ultralow jitter

Two-Channel Simultaneously Sampling ADC

73.2dB SNR

90dB SFDR

Low Power: 95mW/67mW/50mW Total

48mW/34mW/25mW per Channel

Single 1.8V Supply

of0.08ps

allowsundersamplingofIFfrequencieswith

CMOS, DDR CMOS, or DDR LVDS Outputs

RMS

excellent noise performance.

Selectable Input Ranges: 1V to 2V

P-P

750MHz Full Power Bandwidth S/H

Optional Data Output Randomizer

Optional Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

Serial SPI Port for Configuration

64-Pin (9mm × 9mm) QFN Package

DC specs include 1LSB INL (typ), 0.3LSB DNL (typ)

and no missing codes over temperature. The transition

noise is 1.2LSB

RMS

The digital outputs can be either full rate CMOS, double

data rate CMOS, or double data rate LVDS. A separate

output power supply allows the CMOS output swing to

range from 1.2V to 1.8V.

APPLICATIONS

–

The ENC and ENC inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An optional clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

Communications

Cellular Base Stations

Software Defined Radios

Portable Medical Imaging

Multi-Channel Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Nondestructive Testing

TYPICAL APPLICATION

2-Tone FFT, f_IN= 70MHz and 69MHz

1.8V

–10

–20

CH 1

ANALOG

INPUT

14-BIT

D1_13

S/H

–30

–40

–50

–60

–70

ADC CORE

CMOS,

DDR CMOS,

DDR LVDS

OUTPUTS

D1_0

D2_13

OUTPUT

DRIVERS

CH 2

ANALOG

INPUT

14-BIT

ADC CORE

–80

–90

D2_0

–100

–110

–120

65MHz

CLOCK

CONTROL

FREQUENCY (MHz)

21421014 TA01b

21421014 TA01a

GND

OGND

21421014fa

12 3 4 5 6 7...38

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