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LTC1750CFW#TRPBF PDF预览

LTC1750CFW#TRPBF

更新时间: 2024-02-12 09:48:05
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凌特 - Linear /
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20页 277K
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LTC1750CFW#TRPBF 数据手册

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LTC1750  
14-Bit, 80Msps  
Wide Bandwidth ADC  
U
FEATURES  
DESCRIPTIO  
Sample Rate: 80Msps  
The LTC®1750 is an 80Msps, 14-bit A/D converter de-  
signed for digitizing wide dynamic range signals up to  
frequencies of 500MHz. The input range of the ADC can be  
optimized with the on-chip PGA sample-and-hold circuit  
and flexible reference circuitry.  
500MHz Full Power Bandwidth S/H  
Direct IF Sampling Up to 500MHz  
PGA Front End (2.25VP-P or 1.35VP-P Input Range)  
75.5dB SNR and 90dB SFDR (PGA = 0)  
73dB SNR and 90dB SFDR (PGA = 1)  
The LTC1750 has a highly linear sample-and-hold circuit  
with a bandwidth of 500MHz. The SFDR is 82dB with an  
input frequency of 250MHz. Ultralow jitter of 0.12psRMS  
allows undersampling of IF frequencies with minimal  
degradation in SNR. DC specs include ±3LSB INL and no  
missing codes.  
No Missing Codes  
Single 5V Supply  
Power Dissipation: 1.45W  
Two Pin Selectable Reference Values  
Two’s Complement or Offset Binary Outputs  
Out-of-Range Indicator  
The digital interface is compatible with 5V, 3V, 2V and  
LVDS logic systems. The ENC and ENC inputs may be  
driven differentially from PECL, GTL and other low swing  
logic families or from single-ended TTL or CMOS. The low  
noise, high gain ENC and ENC inputs may also be driven  
by a sinusoidal signal without degrading performance. A  
separate output power supply can be operated from 0.5V  
to 5V, making it easy to connect directly to any low voltage  
DSPs or FIFOs.  
Data Ready Output Clock  
Pin-for-Pin Family  
48-Pin TSSOP Package  
U
APPLICATIO S  
Telecommunications  
Receivers  
Cellular Base Stations  
Spectrum Analysis  
The 48-pin TSSOP package with a flow-through pinout  
simplifies the board layout.  
Imaging Systems  
MRI  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
Tomography  
W
BLOCK DIAGRA  
80Msps, 14-Bit ADC with a 2.25V Differential Input Range  
OV  
DD  
PGA  
0.5V TO 5V  
0.1µF  
0.1µF  
+
A
OF  
D13  
IN  
CORRECTION  
LOGIC AND  
SHIFT  
±1.125V  
14  
S/H  
CIRCUIT  
14-BIT  
PIPELINED ADC  
OUTPUT  
LATCHES  
DIFFERENTIAL  
A
ANALOG INPUT  
IN  
D0  
CLKOUT  
REGISTER  
SENSE  
OGND  
BUFFER  
V
DD  
5V  
1µF  
RANGE  
SELECT  
1µF  
1µF  
DIFF AMP  
V
CM  
GND  
2V  
REF  
CONTROL LOGIC  
4.7µF  
1750 BD  
REFLB REFHA  
4.7µF  
REFLA REFHB  
ENC  
ENC MSBINV  
0.1µF  
1µF  
0.1µF  
1µF  
DIFFERENTIAL  
ENCODE INPUT  
1750f  
1

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