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LTC1264-7C PDF预览

LTC1264-7C

更新时间: 2024-11-10 22:34:31
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
12页 302K
描述
Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter

LTC1264-7C 数据手册

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LTC1264-7  
Linear Phase, Group Delay  
Equalized, 8th Order  
Lowpass Filter  
U
DESCRIPTIO  
EATURE  
S
F
Steeper Roll-Off Than Bessel Filters  
High Speed: fC 200kHz  
Phase Equalized Filter in a 14-Pin Package  
Phase and Group Delay Response Fully Tested  
Transient Response Exhibits 5% Overshoot and  
No Ringing  
The LTC1264-7 is a clock-tunable monolithic 8th order  
lowpass filter with linear passband phase and flat group  
delay. The amplitude response approximates a maximally  
flat passband and exhibits steeper roll-off than an equiva-  
lent 8th order Bessel filter. For instance, at twice the cutoff  
frequency the filter attains 28dB attenuation (vs 12dB for  
Bessel), while at three times the cutoff frequency the filter  
attains 55dB attenuation (vs 30dB for Bessel). The cutoff  
frequencyoftheLTC1264-7istunedviaanexternalTTLor  
CMOS clock.  
65dB THD or Better Throughout a 100kHz Passband  
No External Components Needed  
O U  
PPLICATI  
S
A
The clock-to-cutoff frequency ratio of the LTC1264-7 can  
be set to 25:1 (pin 10 to V+) or 50:1 (pin 10 to V).  
Data Communication Filters  
Time Delay Networks  
Phase Matched Filters  
When the filter operates at clock-to-cutoff frequency ratio  
of 25:1, the input is double-sampled to lower the risk of  
aliasing.  
The LTC1264-7 is optimized for speed. Depending on the  
operating conditions, cutoff frequencies between 200kHz  
and250kHzcanbeobtained.(PleaserefertothePassband  
vs Clock Frequency graphs.)  
The LTC1264-7 is pin-compatible with the LTC1064-X  
series.  
U
O
TYPICAL APPLICATI  
4-Level PAM Eye Diagram  
200kHz Linear Phase Lowpass Filter  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
V
IN  
–8V  
LTC1264-7  
f
= 5MHz  
8V  
CLK  
8V  
V
OUT  
8
1264-7 TA01  
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A  
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED  
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE  
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT  
1264-7 TA02  
500ns/DIV  
PIN AND THE f  
LINE.  
fCLK = 5MHz  
CLK  
f
C = 200kHz  
1

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