Datasheet > LS1048ASE7PTA

LS1048ASE7PTA

更新时间： 2024-11-12 19:02:39

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
2页	146K
描述
Multifunction Peripheral

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中文翻译

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技术参数
数据手册

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LS1048ASE7PTA 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.62	湿度敏感等级：	3
峰值回流温度（摄氏度）：	250	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

LS1048ASE7PTA 数据手册

QorIQ LS1

Processor

Family

QorIQ LS1088A and LS1048A

Communications Processors

Enabling the intelligent edge with NXP’s next generation DPAA2 data path

architecture and ARM v8 64-bit processors.

TARGET APPLICATIONS

The ARM^®general-purpose processors and DPAA2 are

supported by a powerful software toolkit that provides a higher

level of hardware abstraction and makes software development

quick and simple. This combination balances ease-of-use with

high-performance processing in a Linux^®environment that

is familiar to any software programmer. Customers can fully

exploit the underlying hardware and easily adapt to network

changes for real-time ‘soft’ control over the network.

} Intelligent edge access

} NFV solutions

} Wireless access point control

} Virtual CPE

} iNIC

} Industrial

SOFTWARE TOOLKIT

OVERVIEW

NXP has significant and increasing global investment in software

for the embedded marketplace. The NXP software development

kit (SDK) delivers foundational technologies (user space, fast

path, virtualization) that are continuously ‘upstreamed’ to

support the networking portfolio. With 13+ years experience

of commercial ARM software tooling, operating system

development and delivery, NXP continues to be a strong

The QorIQ LS10x8A family of multicore communications

processors combines up to eight ARM^®Cortex^®-A53 cores

with the advanced, high-performance datapath and network

peripheral interfaces required for wireless access points,

networking infrastructure and intelligent edge access,

including virtual customer premise equipment (vCPE), and

high-performance industrial applications.

The QorIQ LS10x8A processors include NXP’s second-

generation datapath acceleration architecture (DPAA2).

DPAA2 provides the infrastructure required to support

simplified and secure networking interface and accelerator

sharing by multiple general-purpose CPU cores, while also

providing a range of powerful acceleration engines to

offload software running on the CPUs.

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