Datasheet > LS1046AXE8Q1A

LS1046AXE8Q1A

更新时间： 2024-03-03 10:08:44

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
194页	2019K
描述
Layerscape 64-bit Arm Cortex-A72, Quad-core, 1.6GHz, -40 to 105C, Security enabled

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LS1046AXE8Q1A 数据手册

Revision history

Table 145. Revision history

Revision

Date

Description

06/2020

• In Table 4

• Updated recommended value of USB_SV_INfrom "0.3 to USB_SV_DD" to "GND to

USB_SV_DD

• Added note 10 for available temperature range for part numbers

• Removed input signals from Table 5 as they are irrelevant for output drive capability

• Removed typo "PORESET_B assertion" from step2 of secure boot fuse programming in

Power sequencing

• In Table 7 and Table 8

• Added note 9 regarding power numbers applicability

• Added power numbers for 1200MHz at 1.0V

• Added note 10 regarding power numbers applicability for 1200MHz at 1.0V

• In Table 9

• Added column for Core Frequency = 1.2 GHz (VDD =1.0V)

• For PH20 mode, corrected "run to PH20 state" as "PW15 to PH20 state"

• For LPM20, corrected "PH20 to LPM20" as "PW15 to LPM20"

• Added note 2 regarding extended temperature range in Table 144

07/2019

05/2019

• Updated Figure 80

• In Pinout list,

• added note 27, 28

• changed the note reference of "D1_MALERT_B" signal from 6 to 27

• changed the note reference of "HRESET_B" signal from 6 to 28

• Removed switchable from I2C/DUART and EVDD

• updated Warning

• Removed section "General AC timing specifications"

• Removed note 1 "Caution: The relevant clock ratio settings must be chosen such that the

resulting SYSCLK frequencies do not exceed their respective maximum or minimum operating

frequencies." from Table 14

• Removed note 1 and 2 from Table 16

• Added Figure 11

• Added notes 6 and 7 in Table 23

• Added note 3 in Table 72

• In Table 89,

• added a new column Notes

• updated "CS to SCK delay" and "After SCK delay" parameters

• removed "SCK cycle time" parameter

• Updated section QSPI AC timing specifications

• In section QSPI timing SDR mode,

• updated "CS output hold time" and "CS output delay" parameters in Table 91

• added a note below the table

• Updated Figure 61

• Updated section Temperature diode

• Removed jitter specs of GTX_CLK125 from Table 18

• Added note in Power sequencing

03/2018

• In Features, updated two to three for SGMII interfaces supporting 2500 Mbps

• Updated Figure 92

• In Power sequencing, updated 10 ms to 95 ms in second bullet point

• In Table 9, updated PW20 to PH20 and PCL10 to PH20

• In Table 10, updated X1VDD to XVDD and PROG_SFP to TA_PROG_SFP

• Updated Figure 1 and Figure 2 to show 8 MACs

• In Table 12, updated PROG_SFP to TA_PROG_SFP

• Updated Real-time clock timing (RTC)

• Updated rise/fall time spec to 0.75ns and removed 0.54ns from Table 18 and Table 52

• Removed Clock period jitter (peak to peak) row from Table 22

• Updated first row of Table 23

Table continues on the next page...

QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020

192

NXP Semiconductors

1...189 190 191192193 194

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与LS1046AXE8Q1A相关器件

型号	品牌	描述	获取价格	数据表
LS1046AXE8T1A	NXP	Layerscape 64-bit Arm Cortex-A72, Quad-core, 1.8GHz, -40 to 105C, Security enabled	获取价格
LS1046AXN8P1A	NXP	Layerscape 64-bit Arm Cortex-A72, Quad-core, 1.4GHz, -40 to 105C, Security disabled	获取价格
LS1046AXN8Q1A	NXP	Layerscape 64-bit Arm Cortex-A72, Quad-core, 1.6GHz, -40 to 105C, Security disabled	获取价格
LS1046AXN8T1A	NXP	Layerscape 64-bit Arm Cortex-A72, Quad-core, 1.8GHz, -40 to 105C, Security disabled	获取价格
LS1048ASE7MQA	NXP	Multifunction Peripheral	获取价格
LS1048ASE7PTA	NXP	Multifunction Peripheral	获取价格

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