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LPR520 PDF预览

LPR520

更新时间: 2024-11-27 22:24:43
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逻辑 - LOGIC /
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5页 164K
描述
4 x 16-bit Multilevel Pipeline Register

LPR520 数据手册

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LPR520  
4 x 16-bit Multilevel Pipeline Register  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The LPR520 is functionally compat-  
The S1-0 select lines control a 4-to-1  
ible with the L29C520 but have 16-bit multiplexer which routes the contents  
Four 16-bit Registers  
Implements Double 2-Stage  
Pipeline or Single 4-Stage Pipeline  
Register  
inputs and outputs. The LPR520 is  
implemented in low power CMOS.  
of any of the registers to the Y output  
pins. The independence of the I and S  
controls allows simultaneous write  
and read operations on different  
registers.  
Hold, Shift, and Load Instructions  
The LPR520 contains four registers  
Separate Data In and Data Out Pins which can be configured as two  
independent, 2-level pipelines or as  
one 4-level pipeline.  
High-Speed, Low Power CMOS  
Technology  
Three-State Outputs  
44-pin PLCC, J-Lead  
The Instruction pins, I1-0, control the  
loading of the registers. The registers  
may be configured as a four-stage  
delay line, with data loaded into R1  
and shifted sequentially through R2,  
R3, and R4. Also, data may be loaded  
from the inputs into either R1 or R3  
with only R2 or R4 shifting. Finally,  
I1-0 may be set to prevent any register  
from changing.  
TABLE 1.  
LPR520 BLOCK DIAGRAM  
LPR520 INSTRUCTION TABLE  
I1 I0 Description  
16  
L
L
L
H
L
DR1 R1R2 R2R3 R3R4  
D15-0  
HOLD HOLD  
DR3  
R3R4  
REG 1  
H
H
DR1 R1R2 HOLD  
HOLD  
16  
REG 2  
Y15-0  
H
ALL REGISTERS ON HOLD  
REG 3  
REG 4  
OE  
2
S1-0  
TABLE 2. OUTPUT SELECT  
S1 S0 Register Selected  
L
L
L
H
L
Register 4  
Register 3  
Register 2  
Register 1  
2
I1-0  
CLK  
H
H
H
Pipeline Registers  
08/02/2000–LDS.P520-C  
1

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