LPC43S6x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
System tick timer.
Cortex-M0 Processor core
ARM Cortex-M0 co-processor (version r0p0) capable of off-loading the main ARM
Cortex-M4 application processor.
Running at frequencies of up to 204 MHz.
JTAG
Built-in NVIC.
Cortex-M0 subsystem
ARM Cortex-M0 coprocessor controlling the SPI and SGPIO residing on a
separate AHB multilayer matrix. Includes 2 kB + 16 kB of SRAM.
Running at frequencies of up to 204 MHz.
Connected via a core-to-core bridge to the main AHB multilayer matrix and the
main ARM Cortex-M4 processor.
JTAG and built-in NVIC.
On-chip memory
Up to 1 MB on-chip dual bank flash memory with flash accelerator.
16 kB on-chip EEPROM data memory.
154 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
64-bit of One-Time Programmable (OTP) memory for general-purpose use.
Two banks (256-bit total) of One-Time Programmable (OTP) memory for AES key
storage. One bank can store an encrypted key for decoding the boot image.
AES engine for encryption and decryption of the boot image and data with DMA
support and programmable via a ROM-based API.
Configurable digital peripherals
Serial GPIO (SGPIO) interface.
SCTimer/PWM subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.
Serial interfaces
Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
USB interface electrical test software included in ROM USB stack.
One 550 UART with DMA support and full modem interface.
Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
Up to two C_CAN 2.0B controllers with one channel each.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
LPC43S6X
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© NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet
Rev. 1.3 — 13 January 2020
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