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LPC11E67JBD64,551 PDF预览

LPC11E67JBD64,551

更新时间: 2024-01-25 14:38:47
品牌 Logo 应用领域
恩智浦 - NXP 时钟微控制器外围集成电路
页数 文件大小 规格书
90页 1383K
描述
RISC Microcontroller, 32-Bit, FLASH, CMOS, PQFP64

LPC11E67JBD64,551 技术参数

生命周期:Active包装说明:LFQFP,
Reach Compliance Code:unknown风险等级:5.76
具有ADC:YES地址总线宽度:
位大小:32最大时钟频率:25 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:JESD-30 代码:S-PQFP-G64
长度:10 mmI/O 线路数量:50
端子数量:64PWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
ROM可编程性:FLASH座面最大高度:1.6 mm
速度:50 MHz最大供电电压:3.6 V
最小供电电压:2.4 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:10 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

LPC11E67JBD64,551 数据手册

 浏览型号LPC11E67JBD64,551的Datasheet PDF文件第2页浏览型号LPC11E67JBD64,551的Datasheet PDF文件第3页浏览型号LPC11E67JBD64,551的Datasheet PDF文件第4页浏览型号LPC11E67JBD64,551的Datasheet PDF文件第5页浏览型号LPC11E67JBD64,551的Datasheet PDF文件第6页浏览型号LPC11E67JBD64,551的Datasheet PDF文件第7页 
LPC11E6x  
32-bit ARM Cortex-M0+ microcontroller; up to 256 kB flash  
and 36 kB SRAM; 4 kB EEPROM; 12-bit ADC  
Rev. 1.3 — 8 September 2016  
Product data sheet  
1. General description  
The LPC11E6x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at  
CPU frequencies of up to 50 MHz. The LPC11E6x support up to 256 KB of flash memory,  
a 4 KB EEPROM, and 36 KB of SRAM.  
The ARM Cortex-M0+ is an easy-to-use, energy-efficient core using a two-stage pipeline  
and fast single-cycle I/O access.  
The peripheral complement of the LPC11E6x includes a DMA controller, a CRC engine,  
two I2C-bus interfaces, up to five USARTs, two SSP interfaces, PWM/timer subsystem  
with six configurable multi-purpose timers, a Real-Time Clock, one 12-bit ADC,  
temperature sensor, function-configurable I/O ports, and up to 80 general-purpose I/O  
pins.  
For additional documentation related to the LPC11E6x parts, see Section 18  
“References”.  
2. Features and benefits  
System:  
ARM Cortex-M0+ processor (version r0p1), running at frequencies of up to 50 MHz  
with single-cycle multiplier and fast single-cycle I/O port.  
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  
AHB Multilayer matrix.  
System tick timer.  
Serial Wire Debug (SWD) and JTAG boundary scan modes supported.  
Micro Trace Buffer (MTB) supported.  
Memory:  
Up to 256 KB on-chip flash programming memory with page erase.  
Up to 32 KB main SRAM.  
Up to two additional SRAM blocks of 2 KB each.  
Up to 4 KB EEPROM.  
ROM API support:  
Boot loader.  
USART drivers.  
I2C drivers.  
DMA drivers.  
Power profiles.  
Flash In-Application Programming (IAP) and In-System Programming (ISP).  

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