Datasheet > LPC11U12FHN33

LPC11U12FHN33

更新时间： 2024-02-03 16:31:29

品牌	Logo	应用领域
恩智浦 - NXP		闪存微控制器静态存储器
页数	文件大小	规格书
64页	898K
描述
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; 6 kB SRAM; USB device; USART

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数据手册

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LPC11U12FHN33 数据手册

LPC11U1x

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; 6 kB

SRAM; USB device; USART

Rev. 1 — 11 April 2011

Objective data sheet

1. General description

The LPC11U1x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11U1x operate at CPU frequencies of up to 50 MHz.

Equipped with a highly flexible and configurable Full Speed USB 2.0 device controller, the

LPC11U1x brings unparalleled design flexibility and seamless integration to today’s

demanding connectivity solutions.

The peripheral complement of the LPC11U1x includes up to 32 kB of flash memory, 6 kB

of SRAM data memory, one Fast-mode Plus I²C-bus interface, one RS-485/EIA-485

USART with support for synchronous mode and smart card interface, two SSP interfaces,

four general purpose counter/timers, a 10-bit ADC, and up to 40 general purpose I/O pins.

2. Features and benefits

System:

ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Non Maskable Interrupt (NMI) input selectable from several input sources.

System tick timer.

Memory:

Up to 32 kB on-chip flash program memory.

Total of 6 kB SRAM data memory (4 kB main SRAM and 2 kB USB SRAM).

16 kB boot ROM.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

Debug options:

Standard JTAG test/debug interface.

Serial Wire Debug.

Boundary scan for simplified board testing.

Digital peripherals:

Up to 40 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, repeater mode, and open-drain mode.

Up to 8 GPIO pins can beselected as edge and level sensitive interrupt sources.

12 3 4 5 6 7...64

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